x86 queue, 2019-12-16
Feature: * Cooperlake CPU model Cleanups: * Use g_autofree in a few places -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEEWjIv1avE09usz9GqKAeTb5hNxaYFAl333NMUHGVoYWJrb3N0 QHJlZGhhdC5jb20ACgkQKAeTb5hNxaak0A//WoBGtw3WffuzB988oK3214gxzUmb jHq3gI3ZJ2eAy5adq7PbWMhLHn+VBJLz5OCgMuaZ/pOpMp5WmMfB128evdoj01EP jKk2kP+GNsjfPWKuDpQy3hnuXV/74Y+sxh122y01/atU7aai2wlOyx/OKA3ZGVxf schKPDT+xCBbbEqLxNh0vdKy49xE8X4J8YLPrx0ZZJIn0crPjaZiLU9Seq3j3cu/ DfXGrf7BU1fAe9wXL1PfYQYLc7Gpj6quC1gpKW3/Dh4lytkarUHsURybDqj8FwQP FLIlSLsHeFWvt6n3s4JfJ0frtG33Tx16QN89Cda8KhFGISXBuWSkdZ5zrIi5sfD+ EoxsIxNmsnDszHUyV1gXDKmbHnGYGfgPAzsN7IGpChvtZhrkPwbx5V7wu/jr324j HL4h+k2KgIQjfCfC/pcO1zvLrQWaDZEIEQo4aa6IHIS4bUYsjGlkaXyNjPSM0QFT RUprnL7yBLPYMq5CdiCnoqMZNWyi+MBEXye+AA0V4DYUUdvSWk1H8+pFjd73nIC9 +j9qQ8N78v5cLMsU/5fV44lsFvNCjCvC2T6ydCtv8y8IjkCUVVv2YBqQZ/BpcUlL 1D3dbghj3qFFhsa1ZXhjXkfCdGzd+BVn42lIq1epeDiLJ7Uz8KXRbqn6qG/x8Nwf TzUzb5KiXhMCeDo= =oyaO -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging x86 queue, 2019-12-16 Feature: * Cooperlake CPU model Cleanups: * Use g_autofree in a few places # gpg: Signature made Mon 16 Dec 2019 19:36:51 GMT # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-pull-request: i386: Use g_autofree in a few places i386: Add new CPU model Cooperlake i386: Add macro for stibp i386: Add MSR feature bit for MDS-NO Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
e98e5c35d8
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@ -1671,11 +1671,8 @@ static char *x86_cpu_type_name(const char *model_name)
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static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename = x86_cpu_type_name(cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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return oc;
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g_autofree char *typename = x86_cpu_type_name(cpu_model);
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return object_class_by_name(typename);
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}
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static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
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@ -3159,6 +3156,66 @@ static X86CPUDefinition builtin_x86_defs[] = {
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{ /* end of list */ }
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}
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},
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{
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.name = "Cooperlake",
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.level = 0xd,
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.vendor = CPUID_VENDOR_INTEL,
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.family = 6,
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.model = 85,
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.stepping = 10,
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.features[FEAT_1_EDX] =
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CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
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CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
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CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
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CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
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CPUID_DE | CPUID_FP87,
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.features[FEAT_1_ECX] =
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CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
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CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
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CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
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CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
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CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
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CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
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.features[FEAT_8000_0001_EDX] =
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CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
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CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
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.features[FEAT_8000_0001_ECX] =
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CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
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.features[FEAT_7_0_EBX] =
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CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
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CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
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CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
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CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
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CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
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CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
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.features[FEAT_7_0_ECX] =
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CPUID_7_0_ECX_PKU |
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CPUID_7_0_ECX_AVX512VNNI,
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.features[FEAT_7_0_EDX] =
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CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
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CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
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.features[FEAT_ARCH_CAPABILITIES] =
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MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
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MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO,
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.features[FEAT_7_1_EAX] =
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CPUID_7_1_EAX_AVX512_BF16,
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/*
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* Missing: XSAVES (not supported by some Linux versions,
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* including v4.1 to v4.12).
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* KVM doesn't yet expose any XSAVES state save component,
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* and the only one defined in Skylake (processor tracing)
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* probably will block migration anyway.
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*/
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.features[FEAT_XSAVE] =
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CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
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CPUID_XSAVE_XGETBV1,
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.features[FEAT_6_EAX] =
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CPUID_6_EAX_ARAT,
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.xlevel = 0x80000008,
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.model_id = "Intel Xeon Processor (Cooperlake)",
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},
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{
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.name = "Icelake-Client",
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.level = 0xd,
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@ -4166,7 +4223,6 @@ static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
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CPUX86State *env = &cpu->env;
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FeatureWordInfo *f = &feature_word_info[w];
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int i;
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char *feat_word_str;
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if (!cpu->force_features) {
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env->features[w] &= ~mask;
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@ -4179,13 +4235,12 @@ static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
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for (i = 0; i < 64; ++i) {
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if ((1ULL << i) & mask) {
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feat_word_str = feature_word_description(f, i);
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g_autofree char *feat_word_str = feature_word_description(f, i);
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warn_report("%s: %s%s%s [bit %d]",
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verbose_prefix,
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feat_word_str,
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f->feat_names[i] ? "." : "",
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f->feat_names[i] ? f->feat_names[i] : "", i);
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g_free(feat_word_str);
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}
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}
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}
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@ -4687,17 +4742,14 @@ static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
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ObjectClass *class_b = (ObjectClass *)b;
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X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
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X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
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char *name_a, *name_b;
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int ret;
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if (cc_a->ordering != cc_b->ordering) {
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ret = cc_a->ordering - cc_b->ordering;
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} else {
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name_a = x86_cpu_class_get_model_name(cc_a);
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name_b = x86_cpu_class_get_model_name(cc_b);
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g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
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g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
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ret = strcmp(name_a, name_b);
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g_free(name_a);
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g_free(name_b);
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}
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return ret;
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}
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@ -4735,9 +4787,9 @@ static void x86_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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X86CPUClass *cc = X86_CPU_CLASS(oc);
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char *name = x86_cpu_class_get_model_name(cc);
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char *desc = g_strdup(cc->model_description);
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char *alias_of = x86_cpu_class_get_alias_of(cc);
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g_autofree char *name = x86_cpu_class_get_model_name(cc);
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g_autofree char *desc = g_strdup(cc->model_description);
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g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
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if (!desc && alias_of) {
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if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
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@ -4751,9 +4803,6 @@ static void x86_cpu_list_entry(gpointer data, gpointer user_data)
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}
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qemu_printf("x86 %-20s %-48s\n", name, desc);
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g_free(name);
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g_free(desc);
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g_free(alias_of);
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}
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/* list available CPU models and flags */
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@ -5192,7 +5241,7 @@ static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
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static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
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{
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char *typename = x86_cpu_type_name(name);
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g_autofree char *typename = x86_cpu_type_name(name);
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TypeInfo ti = {
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.name = typename,
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.parent = TYPE_X86_CPU,
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@ -5201,14 +5250,12 @@ static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
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};
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type_register(&ti);
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g_free(typename);
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}
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static void x86_register_cpudef_types(X86CPUDefinition *def)
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{
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X86CPUModel *m;
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const X86CPUVersionDefinition *vdef;
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char *name;
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/* AMD aliases are handled at runtime based on CPUID vendor, so
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* they shouldn't be set on the CPU model table.
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for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
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X86CPUModel *m = g_new0(X86CPUModel, 1);
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g_autofree char *name =
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x86_cpu_versioned_model_name(def, vdef->version);
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m->cpudef = def;
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m->version = vdef->version;
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name = x86_cpu_versioned_model_name(def, vdef->version);
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x86_register_cpu_model_type(name, m);
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g_free(name);
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if (vdef->alias) {
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X86CPUModel *am = g_new0(X86CPUModel, 1);
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if (xcc->host_cpuid_required) {
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if (!accel_uses_host_cpuid()) {
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char *name = x86_cpu_class_get_model_name(xcc);
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g_autofree char *name = x86_cpu_class_get_model_name(xcc);
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error_setg(&local_err, "CPU model '%s' requires KVM", name);
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g_free(name);
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goto out;
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}
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@ -6422,10 +6468,9 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
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/* Cache information initialization */
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if (!cpu->legacy_cache) {
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if (!xcc->model || !xcc->model->cpudef->cache_info) {
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char *name = x86_cpu_class_get_model_name(xcc);
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g_autofree char *name = x86_cpu_class_get_model_name(xcc);
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error_setg(errp,
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"CPU model '%s' doesn't support legacy-cache=off", name);
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g_free(name);
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return;
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}
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env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
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@ -771,6 +771,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
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/* Speculation Control */
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#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
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/* Single Thread Indirect Branch Predictors */
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#define CPUID_7_0_EDX_STIBP (1U << 27)
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/* Arch Capabilities */
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#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
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/* Core Capability */
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@ -838,6 +840,7 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define MSR_ARCH_CAP_RSBA (1U << 2)
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#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
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#define MSR_ARCH_CAP_SSB_NO (1U << 4)
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#define MSR_ARCH_CAP_MDS_NO (1U << 5)
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#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
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