tcg/ppc: Add support for vector saturated add/subtract
Add support for vector saturated add/subtract using Altivec instructions: VADDSBS, VADDSHS, VADDSWS, VADDUBS, VADDUHS, VADDUWS, and VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBS, VSUBUHS, VSUBUWS. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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@ -163,7 +163,7 @@ extern bool have_altivec;
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#define TCG_TARGET_HAS_shv_vec 0
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#define TCG_TARGET_HAS_cmp_vec 1
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#define TCG_TARGET_HAS_mul_vec 0
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#define TCG_TARGET_HAS_sat_vec 0
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#define TCG_TARGET_HAS_sat_vec 1
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec 0
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#define TCG_TARGET_HAS_cmpsel_vec 0
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@ -471,12 +471,24 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
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#define STVX XO31(231)
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#define STVEWX XO31(199)
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#define VADDSBS VX4(768)
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#define VADDUBS VX4(512)
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#define VADDUBM VX4(0)
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#define VADDSHS VX4(832)
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#define VADDUHS VX4(576)
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#define VADDUHM VX4(64)
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#define VADDSWS VX4(896)
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#define VADDUWS VX4(640)
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#define VADDUWM VX4(128)
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#define VSUBSBS VX4(1792)
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#define VSUBUBS VX4(1536)
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#define VSUBUBM VX4(1024)
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#define VSUBSHS VX4(1856)
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#define VSUBUHS VX4(1600)
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#define VSUBUHM VX4(1088)
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#define VSUBSWS VX4(1920)
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#define VSUBUWS VX4(1664)
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#define VSUBUWM VX4(1152)
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#define VMAXSB VX4(258)
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@ -2844,6 +2856,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
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case INDEX_op_smin_vec:
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case INDEX_op_umax_vec:
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case INDEX_op_umin_vec:
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case INDEX_op_ssadd_vec:
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case INDEX_op_sssub_vec:
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case INDEX_op_usadd_vec:
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case INDEX_op_ussub_vec:
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return vece <= MO_32;
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case INDEX_op_cmp_vec:
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return vece <= MO_32 ? -1 : 0;
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@ -2945,6 +2961,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
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gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
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gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },
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ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },
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usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 },
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sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 },
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ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 },
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umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },
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smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },
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umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },
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@ -2971,6 +2991,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_sub_vec:
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insn = sub_op[vece];
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break;
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case INDEX_op_ssadd_vec:
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insn = ssadd_op[vece];
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break;
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case INDEX_op_sssub_vec:
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insn = sssub_op[vece];
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break;
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case INDEX_op_usadd_vec:
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insn = usadd_op[vece];
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break;
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case INDEX_op_ussub_vec:
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insn = ussub_op[vece];
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break;
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case INDEX_op_smin_vec:
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insn = smin_op[vece];
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break;
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@ -3277,6 +3309,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_andc_vec:
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case INDEX_op_orc_vec:
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case INDEX_op_cmp_vec:
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case INDEX_op_ssadd_vec:
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case INDEX_op_sssub_vec:
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case INDEX_op_usadd_vec:
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case INDEX_op_ussub_vec:
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case INDEX_op_smax_vec:
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case INDEX_op_smin_vec:
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case INDEX_op_umax_vec:
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