target/riscv: check before allocating TCG temps
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200626205917.4545-5-zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200724002807.441147-8-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -20,10 +20,10 @@
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static bool trans_fld(DisasContext *ctx, arg_fld *a)
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static bool trans_fld(DisasContext *ctx, arg_fld *a)
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{
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{
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TCGv t0 = tcg_temp_new();
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gen_get_gpr(t0, a->rs1);
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REQUIRE_FPU;
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVD);
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REQUIRE_EXT(ctx, RVD);
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TCGv t0 = tcg_temp_new();
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gen_get_gpr(t0, a->rs1);
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tcg_gen_addi_tl(t0, t0, a->imm);
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tcg_gen_addi_tl(t0, t0, a->imm);
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tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
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tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
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@ -35,10 +35,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
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static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
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static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
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{
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{
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TCGv t0 = tcg_temp_new();
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gen_get_gpr(t0, a->rs1);
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REQUIRE_FPU;
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVD);
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REQUIRE_EXT(ctx, RVD);
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TCGv t0 = tcg_temp_new();
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gen_get_gpr(t0, a->rs1);
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tcg_gen_addi_tl(t0, t0, a->imm);
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tcg_gen_addi_tl(t0, t0, a->imm);
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tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
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tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
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@ -25,10 +25,10 @@
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static bool trans_flw(DisasContext *ctx, arg_flw *a)
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static bool trans_flw(DisasContext *ctx, arg_flw *a)
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{
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{
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TCGv t0 = tcg_temp_new();
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gen_get_gpr(t0, a->rs1);
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REQUIRE_FPU;
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVF);
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REQUIRE_EXT(ctx, RVF);
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TCGv t0 = tcg_temp_new();
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gen_get_gpr(t0, a->rs1);
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tcg_gen_addi_tl(t0, t0, a->imm);
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tcg_gen_addi_tl(t0, t0, a->imm);
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tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
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tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
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@ -41,11 +41,11 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
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static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
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static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
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{
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{
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVF);
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TCGv t0 = tcg_temp_new();
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TCGv t0 = tcg_temp_new();
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gen_get_gpr(t0, a->rs1);
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gen_get_gpr(t0, a->rs1);
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVF);
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tcg_gen_addi_tl(t0, t0, a->imm);
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tcg_gen_addi_tl(t0, t0, a->imm);
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tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
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tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
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