pit fixes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@781 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
f72e8ff4a6
commit
ec844b96c0
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@ -3,6 +3,7 @@ version 0.5.5:
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- SDL full screen support (initial patch by malc)
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- VGA support on PowerPC PREP
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- VBE fixes (Matthew Mastracci)
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- PIT fixes (aka Win98 hardware probe and timer bug)
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version 0.5.4:
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229
hw/i8254.c
229
hw/i8254.c
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@ -25,14 +25,36 @@
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//#define DEBUG_PIT
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#define RW_STATE_LSB 0
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#define RW_STATE_MSB 1
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#define RW_STATE_WORD0 2
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#define RW_STATE_WORD1 3
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#define RW_STATE_LATCHED_WORD0 4
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#define RW_STATE_LATCHED_WORD1 5
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#define RW_STATE_LSB 1
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#define RW_STATE_MSB 2
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#define RW_STATE_WORD0 3
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#define RW_STATE_WORD1 4
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PITChannelState pit_channels[3];
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typedef struct PITChannelState {
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int count; /* can be 65536 */
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uint16_t latched_count;
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uint8_t count_latched;
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uint8_t status_latched;
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uint8_t status;
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uint8_t read_state;
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uint8_t write_state;
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uint8_t write_latch;
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uint8_t rw_mode;
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uint8_t mode;
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uint8_t bcd; /* not supported */
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uint8_t gate; /* timer start */
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int64_t count_load_time;
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/* irq handling */
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int64_t next_transition_time;
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QEMUTimer *irq_timer;
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int irq;
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} PITChannelState;
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struct PITState {
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PITChannelState channels[3];
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};
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static PITState pit_state;
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
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@ -61,7 +83,7 @@ static int pit_get_count(PITChannelState *s)
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}
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/* get pit output bit */
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int pit_get_out(PITChannelState *s, int64_t current_time)
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static int pit_get_out1(PITChannelState *s, int64_t current_time)
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{
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uint64_t d;
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int out;
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@ -92,6 +114,12 @@ int pit_get_out(PITChannelState *s, int64_t current_time)
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return out;
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}
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int pit_get_out(PITState *pit, int channel, int64_t current_time)
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{
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PITChannelState *s = &pit->channels[channel];
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return pit_get_out1(s, current_time);
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}
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/* return -1 if no transition will occur. */
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static int64_t pit_get_next_transition_time(PITChannelState *s,
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int64_t current_time)
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@ -144,8 +172,10 @@ static int64_t pit_get_next_transition_time(PITChannelState *s,
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}
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/* val must be 0 or 1 */
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void pit_set_gate(PITChannelState *s, int val)
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void pit_set_gate(PITState *pit, int channel, int val)
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{
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PITChannelState *s = &pit->channels[channel];
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switch(s->mode) {
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default:
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case 0:
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@ -173,6 +203,12 @@ void pit_set_gate(PITChannelState *s, int val)
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s->gate = val;
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}
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int pit_get_gate(PITState *pit, int channel)
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{
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PITChannelState *s = &pit->channels[channel];
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return s->gate;
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}
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static inline void pit_load_count(PITChannelState *s, int val)
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{
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if (val == 0)
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@ -182,33 +218,62 @@ static inline void pit_load_count(PITChannelState *s, int val)
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pit_irq_timer_update(s, s->count_load_time);
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}
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/* if already latched, do not latch again */
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static void pit_latch_count(PITChannelState *s)
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{
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if (!s->count_latched) {
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s->latched_count = pit_get_count(s);
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s->count_latched = s->rw_mode;
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}
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}
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static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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PITState *pit = opaque;
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int channel, access;
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PITChannelState *s;
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addr &= 3;
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if (addr == 3) {
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channel = val >> 6;
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if (channel == 3)
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return;
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s = &pit_channels[channel];
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access = (val >> 4) & 3;
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switch(access) {
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case 0:
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s->latched_count = pit_get_count(s);
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s->rw_state = RW_STATE_LATCHED_WORD0;
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break;
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default:
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s->mode = (val >> 1) & 7;
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s->bcd = val & 1;
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s->rw_state = access - 1 + RW_STATE_LSB;
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/* XXX: update irq timer ? */
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break;
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if (channel == 3) {
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/* read back command */
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for(channel = 0; channel < 3; channel++) {
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s = &pit->channels[channel];
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if (val & (2 << channel)) {
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if (!(val & 0x20)) {
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pit_latch_count(s);
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}
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if (!(val & 0x10) && !s->status_latched) {
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/* status latch */
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/* XXX: add BCD and null count */
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s->status = (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) |
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(s->rw_mode << 4) |
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(s->mode << 1) |
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s->bcd;
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s->status_latched = 1;
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}
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}
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}
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} else {
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s = &pit->channels[channel];
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access = (val >> 4) & 3;
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if (access == 0) {
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pit_latch_count(s);
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} else {
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s->rw_mode = access;
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s->read_state = access;
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s->write_state = access;
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s->mode = (val >> 1) & 7;
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s->bcd = val & 1;
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/* XXX: update irq timer ? */
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}
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}
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} else {
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s = &pit_channels[addr];
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switch(s->rw_state) {
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s = &pit->channels[addr];
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switch(s->write_state) {
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default:
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case RW_STATE_LSB:
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pit_load_count(s, val);
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break;
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@ -216,13 +281,12 @@ static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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pit_load_count(s, val << 8);
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break;
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case RW_STATE_WORD0:
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s->write_latch = val;
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s->write_state = RW_STATE_WORD1;
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break;
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case RW_STATE_WORD1:
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if (s->rw_state & 1) {
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pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
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} else {
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s->latched_count = val;
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}
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s->rw_state ^= 1;
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pit_load_count(s, s->write_latch | (val << 8));
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s->write_state = RW_STATE_WORD0;
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break;
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}
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}
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@ -230,33 +294,53 @@ static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
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{
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PITState *pit = opaque;
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int ret, count;
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PITChannelState *s;
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addr &= 3;
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s = &pit_channels[addr];
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switch(s->rw_state) {
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case RW_STATE_LSB:
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case RW_STATE_MSB:
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case RW_STATE_WORD0:
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case RW_STATE_WORD1:
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count = pit_get_count(s);
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if (s->rw_state & 1)
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ret = (count >> 8) & 0xff;
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else
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ret = count & 0xff;
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if (s->rw_state & 2)
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s->rw_state ^= 1;
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break;
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default:
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case RW_STATE_LATCHED_WORD0:
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case RW_STATE_LATCHED_WORD1:
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if (s->rw_state & 1)
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ret = s->latched_count >> 8;
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else
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s = &pit->channels[addr];
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if (s->status_latched) {
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s->status_latched = 0;
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ret = s->status;
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} else if (s->count_latched) {
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switch(s->count_latched) {
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default:
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case RW_STATE_LSB:
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ret = s->latched_count & 0xff;
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s->rw_state ^= 1;
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break;
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s->count_latched = 0;
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break;
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case RW_STATE_MSB:
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ret = s->latched_count >> 8;
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s->count_latched = 0;
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break;
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case RW_STATE_WORD0:
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ret = s->latched_count & 0xff;
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s->count_latched = RW_STATE_MSB;
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break;
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}
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} else {
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switch(s->read_state) {
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default:
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case RW_STATE_LSB:
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count = pit_get_count(s);
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ret = count & 0xff;
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break;
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case RW_STATE_MSB:
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count = pit_get_count(s);
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ret = (count >> 8) & 0xff;
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break;
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case RW_STATE_WORD0:
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count = pit_get_count(s);
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ret = count & 0xff;
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s->read_state = RW_STATE_WORD1;
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break;
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case RW_STATE_WORD1:
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count = pit_get_count(s);
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ret = (count >> 8) & 0xff;
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s->read_state = RW_STATE_WORD0;
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break;
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}
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}
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return ret;
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}
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@ -269,7 +353,7 @@ static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
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if (!s->irq_timer)
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return;
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expire_time = pit_get_next_transition_time(s, current_time);
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irq_level = pit_get_out(s, current_time);
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irq_level = pit_get_out1(s, current_time);
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pic_set_irq(s->irq, irq_level);
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#ifdef DEBUG_PIT
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printf("irq_level=%d next_delay=%f\n",
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@ -292,14 +376,21 @@ static void pit_irq_timer(void *opaque)
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static void pit_save(QEMUFile *f, void *opaque)
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{
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PITState *pit = opaque;
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PITChannelState *s;
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int i;
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for(i = 0; i < 3; i++) {
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s = &pit_channels[i];
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s = &pit->channels[i];
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qemu_put_be32s(f, &s->count);
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qemu_put_be16s(f, &s->latched_count);
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qemu_put_8s(f, &s->rw_state);
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qemu_put_8s(f, &s->count_latched);
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qemu_put_8s(f, &s->status_latched);
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qemu_put_8s(f, &s->status);
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qemu_put_8s(f, &s->read_state);
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qemu_put_8s(f, &s->write_state);
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qemu_put_8s(f, &s->write_latch);
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qemu_put_8s(f, &s->rw_mode);
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qemu_put_8s(f, &s->mode);
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qemu_put_8s(f, &s->bcd);
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qemu_put_8s(f, &s->gate);
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@ -313,6 +404,7 @@ static void pit_save(QEMUFile *f, void *opaque)
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static int pit_load(QEMUFile *f, void *opaque, int version_id)
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{
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PITState *pit = opaque;
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PITChannelState *s;
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int i;
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@ -320,10 +412,16 @@ static int pit_load(QEMUFile *f, void *opaque, int version_id)
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return -EINVAL;
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for(i = 0; i < 3; i++) {
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s = &pit_channels[i];
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s = &pit->channels[i];
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qemu_get_be32s(f, &s->count);
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qemu_get_be16s(f, &s->latched_count);
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qemu_get_8s(f, &s->rw_state);
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qemu_get_8s(f, &s->count_latched);
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qemu_get_8s(f, &s->status_latched);
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qemu_get_8s(f, &s->status);
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qemu_get_8s(f, &s->read_state);
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qemu_get_8s(f, &s->write_state);
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qemu_get_8s(f, &s->write_latch);
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qemu_get_8s(f, &s->rw_mode);
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qemu_get_8s(f, &s->mode);
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qemu_get_8s(f, &s->bcd);
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qemu_get_8s(f, &s->gate);
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@ -336,13 +434,14 @@ static int pit_load(QEMUFile *f, void *opaque, int version_id)
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return 0;
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}
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void pit_init(int base, int irq)
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PITState *pit_init(int base, int irq)
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{
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PITState *pit = &pit_state;
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PITChannelState *s;
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int i;
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for(i = 0;i < 3; i++) {
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s = &pit_channels[i];
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s = &pit->channels[i];
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if (i == 0) {
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/* the timer 0 is connected to an IRQ */
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s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
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@ -353,9 +452,9 @@ void pit_init(int base, int irq)
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pit_load_count(s, 0);
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}
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register_savevm("i8254", base, 1, pit_save, pit_load, NULL);
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register_savevm("i8254", base, 1, pit_save, pit_load, pit);
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register_ioport_write(base, 4, 1, pit_ioport_write, NULL);
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register_ioport_read(base, 3, 1, pit_ioport_read, NULL);
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register_ioport_write(base, 4, 1, pit_ioport_write, pit);
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register_ioport_read(base, 3, 1, pit_ioport_read, pit);
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return pit;
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}
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9
hw/pc.c
9
hw/pc.c
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@ -39,6 +39,7 @@ int speaker_data_on;
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int dummy_refresh_clock;
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static fdctrl_t *floppy_controller;
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static RTCState *rtc_state;
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static PITState *pit;
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static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
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{
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@ -169,15 +170,15 @@ static void cmos_init(int ram_size, int boot_device)
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static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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speaker_data_on = (val >> 1) & 1;
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pit_set_gate(&pit_channels[2], val & 1);
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pit_set_gate(pit, 2, val & 1);
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}
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static uint32_t speaker_ioport_read(void *opaque, uint32_t addr)
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{
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int out;
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out = pit_get_out(&pit_channels[2], qemu_get_clock(vm_clock));
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out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
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dummy_refresh_clock ^= 1;
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return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) |
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return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
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(dummy_refresh_clock << 4);
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}
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@ -381,7 +382,7 @@ void pc_init(int ram_size, int vga_ram_size, int boot_device,
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register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
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pic_init();
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pit_init(0x40, 0);
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pit = pit_init(0x40, 0);
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fd = serial_open_device();
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serial_init(0x3f8, 4, fd);
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24
vl.h
24
vl.h
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@ -481,26 +481,12 @@ void pic_info(void);
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#define PIT_FREQ 1193182
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typedef struct PITChannelState {
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int count; /* can be 65536 */
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uint16_t latched_count;
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uint8_t rw_state;
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uint8_t mode;
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uint8_t bcd; /* not supported */
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uint8_t gate; /* timer start */
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int64_t count_load_time;
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/* irq handling */
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int64_t next_transition_time;
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QEMUTimer *irq_timer;
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int irq;
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} PITChannelState;
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typedef struct PITState PITState;
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extern PITChannelState pit_channels[3];
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void pit_init(int base, int irq);
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void pit_set_gate(PITChannelState *s, int val);
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int pit_get_out(PITChannelState *s, int64_t current_time);
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int pit_get_out_edges(PITChannelState *s);
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PITState *pit_init(int base, int irq);
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void pit_set_gate(PITState *pit, int channel, int val);
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int pit_get_gate(PITState *pit, int channel);
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int pit_get_out(PITState *pit, int channel, int64_t current_time);
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/* pc.c */
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void pc_init(int ram_size, int vga_ram_size, int boot_device,
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Reference in a new issue