target/arm: Use new min/max expanders
The generic expanders replace nearly identical code in the translator. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180508151437.4232-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
b87fb8cd9f
commit
ecb8ab8d71
|
@ -6021,15 +6021,18 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
|
|||
tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt);
|
||||
break;
|
||||
case 0x0a: /* SMAXV / UMAXV */
|
||||
tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE,
|
||||
tcg_res,
|
||||
tcg_res, tcg_elt, tcg_res, tcg_elt);
|
||||
if (is_u) {
|
||||
tcg_gen_umax_i64(tcg_res, tcg_res, tcg_elt);
|
||||
} else {
|
||||
tcg_gen_smax_i64(tcg_res, tcg_res, tcg_elt);
|
||||
}
|
||||
break;
|
||||
case 0x1a: /* SMINV / UMINV */
|
||||
tcg_gen_movcond_i64(is_u ? TCG_COND_LEU : TCG_COND_LE,
|
||||
tcg_res,
|
||||
tcg_res, tcg_elt, tcg_res, tcg_elt);
|
||||
break;
|
||||
if (is_u) {
|
||||
tcg_gen_umin_i64(tcg_res, tcg_res, tcg_elt);
|
||||
} else {
|
||||
tcg_gen_smin_i64(tcg_res, tcg_res, tcg_elt);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
|
@ -9927,27 +9930,6 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
|
|||
}
|
||||
}
|
||||
|
||||
/* Helper functions for 32 bit comparisons */
|
||||
static void gen_max_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
|
||||
{
|
||||
tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2, op1, op2);
|
||||
}
|
||||
|
||||
static void gen_max_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
|
||||
{
|
||||
tcg_gen_movcond_i32(TCG_COND_GEU, res, op1, op2, op1, op2);
|
||||
}
|
||||
|
||||
static void gen_min_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
|
||||
{
|
||||
tcg_gen_movcond_i32(TCG_COND_LE, res, op1, op2, op1, op2);
|
||||
}
|
||||
|
||||
static void gen_min_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
|
||||
{
|
||||
tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2);
|
||||
}
|
||||
|
||||
/* Pairwise op subgroup of C3.6.16.
|
||||
*
|
||||
* This is called directly or via the handle_3same_float for float pairwise
|
||||
|
@ -10047,7 +10029,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
|
|||
static NeonGenTwoOpFn * const fns[3][2] = {
|
||||
{ gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 },
|
||||
{ gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 },
|
||||
{ gen_max_s32, gen_max_u32 },
|
||||
{ tcg_gen_smax_i32, tcg_gen_umax_i32 },
|
||||
};
|
||||
genfn = fns[size][u];
|
||||
break;
|
||||
|
@ -10057,7 +10039,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
|
|||
static NeonGenTwoOpFn * const fns[3][2] = {
|
||||
{ gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 },
|
||||
{ gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 },
|
||||
{ gen_min_s32, gen_min_u32 },
|
||||
{ tcg_gen_smin_i32, tcg_gen_umin_i32 },
|
||||
};
|
||||
genfn = fns[size][u];
|
||||
break;
|
||||
|
@ -10512,7 +10494,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
|
|||
static NeonGenTwoOpFn * const fns[3][2] = {
|
||||
{ gen_helper_neon_max_s8, gen_helper_neon_max_u8 },
|
||||
{ gen_helper_neon_max_s16, gen_helper_neon_max_u16 },
|
||||
{ gen_max_s32, gen_max_u32 },
|
||||
{ tcg_gen_smax_i32, tcg_gen_umax_i32 },
|
||||
};
|
||||
genfn = fns[size][u];
|
||||
break;
|
||||
|
@ -10523,7 +10505,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
|
|||
static NeonGenTwoOpFn * const fns[3][2] = {
|
||||
{ gen_helper_neon_min_s8, gen_helper_neon_min_u8 },
|
||||
{ gen_helper_neon_min_s16, gen_helper_neon_min_u16 },
|
||||
{ gen_min_s32, gen_min_u32 },
|
||||
{ tcg_gen_smin_i32, tcg_gen_umin_i32 },
|
||||
};
|
||||
genfn = fns[size][u];
|
||||
break;
|
||||
|
|
Loading…
Reference in a new issue