riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54 RISC-V cores. Currently the sifive_u machine only populates 4 U54 cores. Update the max cpu number to 5 to reflect the real hardware, by creating 2 CPU clusters as containers for RISC-V hart arrays to populate heterogeneous harts. The cpu nodes in the generated DTS have been updated as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -11,7 +11,7 @@
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* 2) PLIC (Platform Level Interrupt Controller)
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*
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* This board currently generates devicetree dynamically that indicates at least
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* two harts.
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* two harts and up to five harts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -34,6 +34,7 @@
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "hw/cpu/cluster.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_plic.h"
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@ -70,6 +71,7 @@ static const struct MemmapEntry {
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static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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uint64_t mem_size, const char *cmdline)
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{
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MachineState *ms = MACHINE(qdev_get_machine());
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void *fdt;
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int cpu;
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uint32_t *cells;
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@ -110,15 +112,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) {
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for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
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int cpu_phandle = phandle++;
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nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]);
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char *isa;
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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SIFIVE_U_CLOCK_FREQ);
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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/* cpu 0 is the management hart that does not have mmu */
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if (cpu != 0) {
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
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} else {
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isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
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}
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
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@ -134,8 +142,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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g_free(nodename);
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}
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cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4);
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for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
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cells = g_new0(uint32_t, ms->smp.cpus * 4);
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for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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@ -153,20 +161,26 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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0x0, memmap[SIFIVE_U_CLINT].base,
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0x0, memmap[SIFIVE_U_CLINT].size);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
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cells, ms->smp.cpus * sizeof(uint32_t) * 4);
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g_free(cells);
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g_free(nodename);
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plic_phandle = phandle++;
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cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4);
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for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
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cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
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for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
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/* cpu 0 is the management hart that does not have S-mode */
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if (cpu == 0) {
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cells[0] = cpu_to_be32(intc_phandle);
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cells[1] = cpu_to_be32(IRQ_M_EXT);
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} else {
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cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
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}
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
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@ -176,7 +190,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
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qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
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cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_PLIC].base,
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0x0, memmap[SIFIVE_U_PLIC].size);
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@ -339,12 +353,31 @@ static void riscv_sifive_u_soc_init(Object *obj)
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MachineState *ms = MACHINE(qdev_get_machine());
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SiFiveUSoCState *s = RISCV_U_SOC(obj);
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object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus),
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TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
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object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
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&error_abort);
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object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
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&error_abort);
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object_initialize_child(obj, "e-cluster", &s->e_cluster,
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sizeof(s->e_cluster), TYPE_CPU_CLUSTER,
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&error_abort, NULL);
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qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
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object_initialize_child(OBJECT(&s->e_cluster), "e-cpus",
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&s->e_cpus, sizeof(s->e_cpus),
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TYPE_RISCV_HART_ARRAY, &error_abort,
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NULL);
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qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
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qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
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qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
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object_initialize_child(obj, "u-cluster", &s->u_cluster,
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sizeof(s->u_cluster), TYPE_CPU_CLUSTER,
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&error_abort, NULL);
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qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
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object_initialize_child(OBJECT(&s->u_cluster), "u-cpus",
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&s->u_cpus, sizeof(s->u_cpus),
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TYPE_RISCV_HART_ARRAY, &error_abort,
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NULL);
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qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
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qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
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qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
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sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
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TYPE_CADENCE_GEM);
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@ -364,7 +397,19 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
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Error *err = NULL;
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NICInfo *nd = &nd_table[0];
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object_property_set_bool(OBJECT(&s->cpus), true, "realized",
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object_property_set_bool(OBJECT(&s->e_cpus), true, "realized",
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&error_abort);
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object_property_set_bool(OBJECT(&s->u_cpus), true, "realized",
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&error_abort);
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/*
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* The cluster must be realized after the RISC-V hart array container,
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* as the container's CPU object is only created on realize, and the
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* CPU must exist and have been parented into the cluster before the
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* cluster is realized.
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*/
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object_property_set_bool(OBJECT(&s->e_cluster), true, "realized",
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&error_abort);
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object_property_set_bool(OBJECT(&s->u_cluster), true, "realized",
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&error_abort);
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/* boot rom */
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@ -430,10 +475,7 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
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{
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mc->desc = "RISC-V Board compatible with SiFive U SDK";
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mc->init = riscv_sifive_u_init;
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/* The real hardware has 5 CPUs, but one of them is a small embedded power
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* management CPU.
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*/
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mc->max_cpus = 4;
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mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
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mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
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mc->default_cpus = mc->min_cpus;
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}
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@ -32,7 +32,10 @@ typedef struct SiFiveUSoCState {
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SysBusDevice parent_obj;
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/*< public >*/
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RISCVHartArrayState cpus;
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CPUClusterState e_cluster;
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CPUClusterState u_cluster;
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RISCVHartArrayState e_cpus;
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RISCVHartArrayState u_cpus;
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DeviceState *plic;
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CadenceGEMState gem;
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} SiFiveUSoCState;
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};
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#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
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#define SIFIVE_U_COMPUTE_CPU_COUNT 4
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#define SIFIVE_U_PLIC_HART_CONFIG "MS"
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#define SIFIVE_U_PLIC_NUM_SOURCES 54
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