Queued target/mips patches
-----BEGIN PGP SIGNATURE----- iQJJBAABCgAzFiEEd0YmQqnvlP0Pdxltupx4Bh3djJsFAllszrMVHGF1cmVsaWVu QGF1cmVsMzIubmV0AAoJELqceAYd3YybB5YP/jz42JzFvL+5iIOGNnQupBwtmgtG NfKwZ/gZZa7ZSUupGfhP1/FIww8NPaWD5XiAFpQZWbVkRVLErrdhQODqblbPhIwY oIUCOrG0ZAspYapMqSpR8BO6xnE2qWUBaQcZpLashfmFFTHpHuTZwliRsyiQo3zh 3NoSS97h3oZ9F2Br+yDN3SN7MtXf9Rd0t6UTqvs1X8AlYV7fUL26bh9Nd2IB+tfu emZDOvUTf+SGPjU91yAPFCfIPJBZa9L6sbV8Kb9hwoiuPTTiFx4KYrgr+JtxzdZ0 nEIYI6PiF03lyJAPpiR8D0uOw6N9u/NzIccz0WcG7G23wfjA1H9iG5S1isYpIeSw kBAqi4QeppJuLTjsyKoqCJD5ilCGE498O0fsZ3vRztNtplHHDpflIVFzkil8wLqU uQ1Uk5Pgi6OKF7OVbxo0OFoF8gzSNRst4SxXiFb2Q2Qsc4aNdljhH2G0YLtuBBr2 RZMo4gYSuoej2SYMX55IgPfTX4ll6OmTdZVZCLs1Y9lAxuuwE6K/BjrtVYJ3l8rb NlIzpZeKWE6t8qqlAbLvD1dF/fzu4rbz0I7qA/LkA/KyMK5rYWRfkLMNVuebmLUE rv1A4fxfQHjA+CBmaaoxk9Ko8k7x43I1C0NsqjeJaalzV5b2xrhXHEayR2VDYUGR ul7UomsYPxvkFKD1 =0ecl -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/aurel/tags/pull-target-mips-20170717' into staging Queued target/mips patches # gpg: Signature made Mon 17 Jul 2017 15:50:27 BST # gpg: using RSA key 0xBA9C78061DDD8C9B # gpg: Good signature from "Aurelien Jarno <aurelien@aurel32.net>" # gpg: aka "Aurelien Jarno <aurelien@jarno.fr>" # gpg: aka "Aurelien Jarno <aurel32@debian.org>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7746 2642 A9EF 94FD 0F77 196D BA9C 7806 1DDD 8C9B * remotes/aurel/tags/pull-target-mips-20170717: target/mips: optimize WSBH, DSBH and DSHD mips: set CP0 Debug DExcCode for SDBBP instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
ed6458726a
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@ -627,6 +627,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
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goto set_DEPC;
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case EXCP_DBp:
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env->CP0_Debug |= 1 << CP0DB_DBp;
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/* Setup DExcCode - SDBBP instruction */
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env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 << CP0DB_DEC;
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goto set_DEPC;
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case EXCP_DDBS:
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env->CP0_Debug |= 1 << CP0DB_DDBS;
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@ -4572,12 +4572,14 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
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case OPC_WSBH:
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{
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_const_tl(0x00FF00FF);
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tcg_gen_shri_tl(t1, t0, 8);
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tcg_gen_andi_tl(t1, t1, 0x00FF00FF);
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tcg_gen_and_tl(t1, t1, t2);
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tcg_gen_and_tl(t0, t0, t2);
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tcg_gen_shli_tl(t0, t0, 8);
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tcg_gen_andi_tl(t0, t0, ~0x00FF00FF);
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tcg_gen_or_tl(t0, t0, t1);
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tcg_temp_free(t2);
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tcg_temp_free(t1);
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tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
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}
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@ -4592,27 +4594,31 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
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case OPC_DSBH:
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{
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_const_tl(0x00FF00FF00FF00FFULL);
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tcg_gen_shri_tl(t1, t0, 8);
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tcg_gen_andi_tl(t1, t1, 0x00FF00FF00FF00FFULL);
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tcg_gen_and_tl(t1, t1, t2);
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tcg_gen_and_tl(t0, t0, t2);
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tcg_gen_shli_tl(t0, t0, 8);
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tcg_gen_andi_tl(t0, t0, ~0x00FF00FF00FF00FFULL);
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tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
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tcg_temp_free(t2);
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tcg_temp_free(t1);
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}
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break;
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case OPC_DSHD:
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{
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_const_tl(0x0000FFFF0000FFFFULL);
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tcg_gen_shri_tl(t1, t0, 16);
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tcg_gen_andi_tl(t1, t1, 0x0000FFFF0000FFFFULL);
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tcg_gen_and_tl(t1, t1, t2);
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tcg_gen_and_tl(t0, t0, t2);
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tcg_gen_shli_tl(t0, t0, 16);
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tcg_gen_andi_tl(t0, t0, ~0x0000FFFF0000FFFFULL);
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tcg_gen_or_tl(t0, t0, t1);
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tcg_gen_shri_tl(t1, t0, 32);
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tcg_gen_shli_tl(t0, t0, 32);
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tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
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tcg_temp_free(t2);
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tcg_temp_free(t1);
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}
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break;
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