riscv: Fix Stage2 SV32 page table walk
As-per RISC-V H-Extension v0.5 draft, the Stage2 SV32 page table has 12bits of VPN[1] and 10bits of VPN[0]. The additional 2bits in VPN[1] is required to handle the 34bit intermediate physical address coming from Stage1 SV32 page table. The 12bits of VPN[1] implies that Stage2 SV32 level-0 page table will be 16KB in size with total 4096 enteries where each entry maps 4MB of memory (same as Stage1 SV32 page table). The get_physical_address() function is broken for Stage2 SV32 level-0 page table because it incorrectly computes output physical address for Stage2 SV32 level-0 page table entry. The root cause of the issue is that get_physical_address() uses the "widened" variable to compute level-0 physical address mapping which changes level-0 mapping size (instead of 4MB). We should use the "widened" variable only for computing index of Stage2 SV32 level-0 page table. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200330082724.120444-1-anup.patel@wdc.com Message-Id: <20200330082724.120444-1-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -559,12 +559,7 @@ restart:
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/* for superpage mappings, make a fake leaf PTE for the TLB's
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benefit. */
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target_ulong vpn = addr >> PGSHIFT;
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if (i == 0) {
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*physical = (ppn | (vpn & ((1L << (ptshift + widened)) - 1))) <<
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PGSHIFT;
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} else {
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*physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT;
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}
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/* set permissions on the TLB entry */
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if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
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