RISC-V: Simplify riscv_cpu_local_irqs_pending
This commit is intended to improve readability. There is no change to the logic. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -35,28 +35,18 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
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}
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#ifndef CONFIG_USER_ONLY
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/*
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* Return RISC-V IRQ number if an interrupt should be taken, else -1.
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* Used in cpu-exec.c
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*
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* Adapted from Spike's processor_t::take_interrupt()
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*/
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static int riscv_cpu_hw_interrupts_pending(CPURISCVState *env)
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static int riscv_cpu_local_irq_pending(CPURISCVState *env)
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{
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target_ulong pending_interrupts = atomic_read(&env->mip) & env->mie;
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target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
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target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
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target_ulong pending = atomic_read(&env->mip) & env->mie;
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target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie);
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target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S && mstatus_sie);
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target_ulong irqs = (pending & ~env->mideleg & -mie) |
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(pending & env->mideleg & -sie);
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target_ulong mie = get_field(env->mstatus, MSTATUS_MIE);
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target_ulong m_enabled = env->priv < PRV_M || (env->priv == PRV_M && mie);
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target_ulong enabled_interrupts = pending_interrupts &
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~env->mideleg & -m_enabled;
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target_ulong sie = get_field(env->mstatus, MSTATUS_SIE);
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target_ulong s_enabled = env->priv < PRV_S || (env->priv == PRV_S && sie);
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enabled_interrupts |= pending_interrupts & env->mideleg &
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-s_enabled;
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if (enabled_interrupts) {
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return ctz64(enabled_interrupts); /* since non-zero */
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if (irqs) {
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return ctz64(irqs); /* since non-zero */
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} else {
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return EXCP_NONE; /* indicates no pending interrupt */
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}
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@ -69,7 +59,7 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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int interruptno = riscv_cpu_hw_interrupts_pending(env);
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int interruptno = riscv_cpu_local_irq_pending(env);
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if (interruptno >= 0) {
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cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
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riscv_cpu_do_interrupt(cs);
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