target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc
Implement the simple 64 bit integer operations from the SIMD scalar 2-register misc group (C3.6.12): the comparisons against zero, plus ABS and NEG. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
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@ -6212,6 +6212,48 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
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tcg_temp_free_i64(tcg_rd);
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tcg_temp_free_i64(tcg_rd);
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}
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}
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static void handle_2misc_64(DisasContext *s, int opcode, bool u,
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TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
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{
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/* Handle 64->64 opcodes which are shared between the scalar and
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* vector 2-reg-misc groups. We cover every integer opcode where size == 3
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* is valid in either group.
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*/
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TCGCond cond;
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switch (opcode) {
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case 0xa: /* CMLT */
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/* 64 bit integer comparison against zero, result is
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* test ? (2^64 - 1) : 0. We implement via setcond(!test) and
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* subtracting 1.
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*/
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cond = TCG_COND_LT;
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do_cmop:
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tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0);
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tcg_gen_neg_i64(tcg_rd, tcg_rd);
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break;
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case 0x8: /* CMGT, CMGE */
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cond = u ? TCG_COND_GE : TCG_COND_GT;
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goto do_cmop;
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case 0x9: /* CMEQ, CMLE */
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cond = u ? TCG_COND_LE : TCG_COND_EQ;
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goto do_cmop;
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case 0xb: /* ABS, NEG */
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if (u) {
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tcg_gen_neg_i64(tcg_rd, tcg_rn);
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} else {
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TCGv_i64 tcg_zero = tcg_const_i64(0);
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tcg_gen_neg_i64(tcg_rd, tcg_rn);
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tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero,
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tcg_rn, tcg_rd);
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tcg_temp_free_i64(tcg_zero);
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}
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break;
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default:
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g_assert_not_reached();
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}
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}
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/* C3.6.12 AdvSIMD scalar two reg misc
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/* C3.6.12 AdvSIMD scalar two reg misc
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* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
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* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
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* +-----+---+-----------+------+-----------+--------+-----+------+------+
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* +-----+---+-----------+------+-----------+--------+-----+------+------+
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@ -6220,7 +6262,50 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
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*/
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*/
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static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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{
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{
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unsupported_encoding(s, insn);
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int opcode = extract32(insn, 12, 5);
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int size = extract32(insn, 22, 2);
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bool u = extract32(insn, 29, 1);
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switch (opcode) {
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case 0xa: /* CMLT */
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if (u) {
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unallocated_encoding(s);
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return;
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}
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/* fall through */
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case 0x8: /* CMGT, CMGE */
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case 0x9: /* CMEQ, CMLE */
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case 0xb: /* ABS, NEG */
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if (size != 3) {
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unallocated_encoding(s);
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return;
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}
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break;
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default:
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/* Other categories of encoding in this class:
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* + floating point (single and double)
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* + SUQADD/USQADD/SQABS/SQNEG : size 8, 16, 32 or 64
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* + SQXTN/SQXTN2/SQXTUN/SQXTUN2/UQXTN/UQXTN2:
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* narrowing saturate ops: size 64/32/16 -> 32/16/8
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*/
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unsupported_encoding(s, insn);
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return;
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}
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if (size == 3) {
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TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
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TCGv_i64 tcg_rd = tcg_temp_new_i64();
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handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn);
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write_fp_dreg(s, rd, tcg_rd);
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tcg_temp_free_i64(tcg_rd);
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tcg_temp_free_i64(tcg_rn);
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} else {
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/* the 'size might not be 64' ops aren't implemented yet */
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g_assert_not_reached();
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}
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}
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}
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/* C3.6.13 AdvSIMD scalar x indexed element
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/* C3.6.13 AdvSIMD scalar x indexed element
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