PPC: convert SPE effective address computation to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5491 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -5316,17 +5316,16 @@ static always_inline void gen_speundef (DisasContext *ctx)
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}
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}
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/* SPE load and stores */
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/* SPE load and stores */
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static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
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static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
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{
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{
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target_long simm = rB(ctx->opcode);
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target_long simm = rB(ctx->opcode);
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if (rA(ctx->opcode) == 0) {
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if (rA(ctx->opcode) == 0)
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tcg_gen_movi_tl(cpu_T[0], simm << sh);
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tcg_gen_movi_tl(EA, simm << sh);
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} else {
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else if (likely(simm != 0))
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tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
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tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh);
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if (likely(simm != 0))
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else
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tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << sh);
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tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
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}
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}
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}
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#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
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#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
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@ -5346,7 +5345,7 @@ static always_inline void gen_evl##name (DisasContext *ctx) \
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GEN_EXCP_NO_AP(ctx); \
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GEN_EXCP_NO_AP(ctx); \
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return; \
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return; \
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} \
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} \
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gen_addr_spe_imm_index(ctx, sh); \
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gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
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op_spe_ldst(spe_l##name); \
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op_spe_ldst(spe_l##name); \
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gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
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gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
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}
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}
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@ -5375,7 +5374,7 @@ static always_inline void gen_evst##name (DisasContext *ctx) \
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GEN_EXCP_NO_AP(ctx); \
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GEN_EXCP_NO_AP(ctx); \
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return; \
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return; \
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} \
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} \
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gen_addr_spe_imm_index(ctx, sh); \
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gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
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gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
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gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
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op_spe_ldst(spe_st##name); \
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op_spe_ldst(spe_st##name); \
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}
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}
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