target-arm: implement CPACR register logic for ARMv7
In ARMv7 the CPACR register allows to control access rights to coprocessor 0-13 interfaces. Bits corresponding to unimplemented coprocessors should be RAZ/WI. Bits ASEDIS, D32DIS, TRCDIS are UNK/SBZP if VFP is not implemented and RAO/WI in some cases. Treating TRCDIS as RAZ/WI since we neither implement a trace macrocell nor a CP14 interface to the trace macrocell registers. Since CPACR bits for VFP/Neon access are honoured with the CPACR_FPEN bit in the TB flags, flushing the TLB is not necessary anymore. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Message-id: 1400532968-30668-1-git-send-email-aggelerf@ethz.ch Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -477,11 +477,35 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
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static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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if (env->cp15.c1_coproc != value) {
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env->cp15.c1_coproc = value;
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/* ??? Is this safe when called from within a TB? */
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tb_flush(env);
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uint32_t mask = 0;
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/* In ARMv8 most bits of CPACR_EL1 are RES0. */
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if (!arm_feature(env, ARM_FEATURE_V8)) {
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/* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
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* ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
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* TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
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*/
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if (arm_feature(env, ARM_FEATURE_VFP)) {
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/* VFP coprocessor: cp10 & cp11 [23:20] */
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mask |= (1 << 31) | (1 << 30) | (0xf << 20);
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if (!arm_feature(env, ARM_FEATURE_NEON)) {
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/* ASEDIS [31] bit is RAO/WI */
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value |= (1 << 31);
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}
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/* VFPv3 and upwards with NEON implement 32 double precision
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* registers (D0-D31).
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*/
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if (!arm_feature(env, ARM_FEATURE_NEON) ||
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!arm_feature(env, ARM_FEATURE_VFP3)) {
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/* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
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value |= (1 << 30);
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}
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}
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value &= mask;
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}
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env->cp15.c1_coproc = value;
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}
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static const ARMCPRegInfo v6_cp_reginfo[] = {
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