hw/arm/armsse: Make number of SRAM banks parameterised
The SSE-200 has four banks of SRAM, each with its own Memory Protection Controller, where the IoTKit has only one. Make the number of SRAM banks a field in ARMSSEInfo. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-10-peter.maydell@linaro.org
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@ -20,11 +20,13 @@
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struct ARMSSEInfo {
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const char *name;
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int sram_banks;
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};
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static const ARMSSEInfo armsse_variants[] = {
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{
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.name = TYPE_IOTKIT,
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.sram_banks = 1,
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},
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};
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@ -118,8 +120,12 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s)
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static void armsse_init(Object *obj)
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{
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ARMSSE *s = ARMSSE(obj);
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ARMSSEClass *asc = ARMSSE_GET_CLASS(obj);
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const ARMSSEInfo *info = asc->info;
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int i;
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assert(info->sram_banks <= MAX_SRAM_BANKS);
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memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX);
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sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
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@ -133,12 +139,17 @@ static void armsse_init(Object *obj)
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TYPE_TZ_PPC);
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sysbus_init_child_obj(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1),
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TYPE_TZ_PPC);
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sysbus_init_child_obj(obj, "mpc", &s->mpc, sizeof(s->mpc), TYPE_TZ_MPC);
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for (i = 0; i < info->sram_banks; i++) {
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char *name = g_strdup_printf("mpc%d", i);
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sysbus_init_child_obj(obj, name, &s->mpc[i],
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sizeof(s->mpc[i]), TYPE_TZ_MPC);
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g_free(name);
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}
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object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate,
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sizeof(s->mpc_irq_orgate), TYPE_OR_IRQ,
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&error_abort, NULL);
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for (i = 0; i < IOTS_NUM_EXP_MPC + 1; i++) {
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for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) {
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char *name = g_strdup_printf("mpc-irq-splitter-%d", i);
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SplitIRQ *splitter = &s->mpc_irq_splitter[i];
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@ -199,6 +210,8 @@ static void armsse_mpcexp_status(void *opaque, int n, int level)
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static void armsse_realize(DeviceState *dev, Error **errp)
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{
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ARMSSE *s = ARMSSE(dev);
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ARMSSEClass *asc = ARMSSE_GET_CLASS(dev);
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const ARMSSEInfo *info = asc->info;
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int i;
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MemoryRegion *mr;
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Error *err = NULL;
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@ -335,35 +348,41 @@ static void armsse_realize(DeviceState *dev, Error **errp)
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qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0,
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qdev_get_gpio_in(dev_splitter, 0));
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/* This RAM lives behind the Memory Protection Controller */
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memory_region_init_ram(&s->sram0, NULL, "armsse.sram0", 0x00008000, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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/* Each SRAM bank lives behind its own Memory Protection Controller */
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for (i = 0; i < info->sram_banks; i++) {
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char *ramname = g_strdup_printf("armsse.sram%d", i);
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SysBusDevice *sbd_mpc;
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memory_region_init_ram(&s->sram[i], NULL, ramname, 0x00008000, &err);
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g_free(ramname);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_link(OBJECT(&s->mpc[i]), OBJECT(&s->sram[i]),
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"downstream", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->mpc[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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/* Map the upstream end of the MPC into the right place... */
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sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]);
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memory_region_add_subregion(&s->container, 0x20000000 + i * 0x8000,
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sysbus_mmio_get_region(sbd_mpc, 1));
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/* ...and its register interface */
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memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000,
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sysbus_mmio_get_region(sbd_mpc, 0));
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}
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object_property_set_link(OBJECT(&s->mpc), OBJECT(&s->sram0),
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"downstream", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->mpc), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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/* Map the upstream end of the MPC into the right place... */
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memory_region_add_subregion(&s->container, 0x20000000,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mpc),
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1));
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/* ...and its register interface */
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memory_region_add_subregion(&s->container, 0x50083000,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mpc),
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0));
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/* We must OR together lines from the MPC splitters to go to the NVIC */
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object_property_set_int(OBJECT(&s->mpc_irq_orgate),
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IOTS_NUM_EXP_MPC + 1, "num-lines", &err);
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IOTS_NUM_EXP_MPC + info->sram_banks,
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"num-lines", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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@ -636,7 +655,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
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}
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/* Wire up the splitters for the MPC IRQs */
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for (i = 0; i < IOTS_NUM_EXP_MPC + 1; i++) {
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for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) {
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SplitIRQ *splitter = &s->mpc_irq_splitter[i];
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DeviceState *dev_splitter = DEVICE(splitter);
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@ -659,7 +678,8 @@ static void armsse_realize(DeviceState *dev, Error **errp)
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"mpcexp_status", i));
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} else {
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/* Splitter input is from our own MPC */
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qdev_connect_gpio_out_named(DEVICE(&s->mpc), "irq", 0,
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qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]),
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"irq", 0,
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qdev_get_gpio_in(dev_splitter, 0));
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qdev_connect_gpio_out(dev_splitter, 0,
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qdev_get_gpio_in_named(dev_secctl,
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@ -90,6 +90,11 @@
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#define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC)
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#define NUM_PPCS (NUM_EXTERNAL_PPCS + 2)
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#define MAX_SRAM_BANKS 4
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#if MAX_SRAM_BANKS > IOTS_NUM_MPC
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#error Too many SRAM banks
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#endif
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typedef struct ARMSSE {
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/*< private >*/
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SysBusDevice parent_obj;
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@ -99,7 +104,7 @@ typedef struct ARMSSE {
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IoTKitSecCtl secctl;
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TZPPC apb_ppc0;
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TZPPC apb_ppc1;
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TZMPC mpc;
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TZMPC mpc[IOTS_NUM_MPC];
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CMSDKAPBTIMER timer0;
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CMSDKAPBTIMER timer1;
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CMSDKAPBTIMER s32ktimer;
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@ -123,7 +128,7 @@ typedef struct ARMSSE {
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MemoryRegion alias1;
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MemoryRegion alias2;
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MemoryRegion alias3;
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MemoryRegion sram0;
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MemoryRegion sram[MAX_SRAM_BANKS];
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qemu_irq *exp_irqs;
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qemu_irq ppc0_irq;
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