target/avr: Introduce basic CPU class object
This patch introduces AVR CPU class object and its basic elements and functions. [AM: Split a larger AVR introduction patch into logical units] Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Co-developed-by: Michael Rolnik <mrolnik@gmail.com> Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk> Signed-off-by: Michael Rolnik <mrolnik@gmail.com> Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> [thuth: Adjusted reset and parent_reset handling] Signed-off-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20200705140315.260514-3-huth@tuxfamily.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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53
target/avr/cpu-qom.h
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53
target/avr/cpu-qom.h
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@ -0,0 +1,53 @@
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/*
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* QEMU AVR CPU
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*
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* Copyright (c) 2016-2020 Michael Rolnik
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#ifndef QEMU_AVR_QOM_H
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#define QEMU_AVR_QOM_H
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#include "hw/core/cpu.h"
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#define TYPE_AVR_CPU "avr-cpu"
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#define AVR_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(AVRCPUClass, (klass), TYPE_AVR_CPU)
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#define AVR_CPU(obj) \
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OBJECT_CHECK(AVRCPU, (obj), TYPE_AVR_CPU)
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#define AVR_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(AVRCPUClass, (obj), TYPE_AVR_CPU)
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/**
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* AVRCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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* @vr: Version Register value.
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*
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* A AVR CPU model.
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*/
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typedef struct AVRCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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DeviceReset parent_reset;
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} AVRCPUClass;
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typedef struct AVRCPU AVRCPU;
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#endif /* !defined (QEMU_AVR_CPU_QOM_H) */
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207
target/avr/cpu.c
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207
target/avr/cpu.c
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@ -0,0 +1,207 @@
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/*
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* QEMU AVR CPU
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*
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* Copyright (c) 2019-2020 Michael Rolnik
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/qemu-print.h"
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#include "exec/exec-all.h"
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#include "cpu.h"
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#include "disas/dis-asm.h"
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static void avr_cpu_set_pc(CPUState *cs, vaddr value)
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{
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AVRCPU *cpu = AVR_CPU(cs);
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cpu->env.pc_w = value / 2; /* internally PC points to words */
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}
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static bool avr_cpu_has_work(CPUState *cs)
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{
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AVRCPU *cpu = AVR_CPU(cs);
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CPUAVRState *env = &cpu->env;
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return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
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&& cpu_interrupts_enabled(env);
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}
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static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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{
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AVRCPU *cpu = AVR_CPU(cs);
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CPUAVRState *env = &cpu->env;
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env->pc_w = tb->pc / 2; /* internally PC points to words */
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}
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static void avr_cpu_reset(DeviceState *ds)
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{
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CPUState *cs = CPU(ds);
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AVRCPU *cpu = AVR_CPU(cs);
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AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
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CPUAVRState *env = &cpu->env;
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mcc->parent_reset(ds);
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env->pc_w = 0;
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env->sregI = 1;
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env->sregC = 0;
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env->sregZ = 0;
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env->sregN = 0;
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env->sregV = 0;
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env->sregS = 0;
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env->sregH = 0;
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env->sregT = 0;
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env->rampD = 0;
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env->rampX = 0;
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env->rampY = 0;
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env->rampZ = 0;
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env->eind = 0;
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env->sp = 0;
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env->skip = 0;
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memset(env->r, 0, sizeof(env->r));
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tlb_flush(cs);
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}
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static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->mach = bfd_arch_avr;
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info->print_insn = NULL;
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}
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static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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mcc->parent_realize(dev, errp);
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}
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static void avr_cpu_set_int(void *opaque, int irq, int level)
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{
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AVRCPU *cpu = opaque;
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CPUAVRState *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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uint64_t mask = (1ull << irq);
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if (level) {
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env->intsrc |= mask;
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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env->intsrc &= ~mask;
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if (env->intsrc == 0) {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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}
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static void avr_cpu_initfn(Object *obj)
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{
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AVRCPU *cpu = AVR_CPU(obj);
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cpu_set_cpustate_pointers(cpu);
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/* Set the number of interrupts supported by the CPU. */
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qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
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sizeof(cpu->env.intsrc) * 8);
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}
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static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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oc = object_class_by_name(cpu_model);
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if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL ||
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object_class_is_abstract(oc)) {
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oc = NULL;
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}
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return oc;
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}
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static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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AVRCPU *cpu = AVR_CPU(cs);
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CPUAVRState *env = &cpu->env;
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int i;
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qemu_fprintf(f, "\n");
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qemu_fprintf(f, "PC: %06x\n", env->pc_w);
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qemu_fprintf(f, "SP: %04x\n", env->sp);
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qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16);
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qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16);
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qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16);
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qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16);
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qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16);
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qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]);
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qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]);
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qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]);
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qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n",
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env->sregI ? 'I' : '-',
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env->sregT ? 'T' : '-',
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env->sregH ? 'H' : '-',
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env->sregS ? 'S' : '-',
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env->sregV ? 'V' : '-',
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env->sregN ? '-' : 'N', /* Zf has negative logic */
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env->sregZ ? 'Z' : '-',
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env->sregC ? 'I' : '-');
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qemu_fprintf(f, "SKIP: %02x\n", env->skip);
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qemu_fprintf(f, "\n");
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for (i = 0; i < ARRAY_SIZE(env->r); i++) {
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qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]);
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if ((i % 8) == 7) {
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qemu_fprintf(f, "\n");
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}
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}
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qemu_fprintf(f, "\n");
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}
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static void avr_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
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mcc->parent_realize = dc->realize;
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dc->realize = avr_cpu_realizefn;
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device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset);
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cc->class_by_name = avr_cpu_class_by_name;
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cc->has_work = avr_cpu_has_work;
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cc->dump_state = avr_cpu_dump_state;
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cc->set_pc = avr_cpu_set_pc;
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cc->disas_set_info = avr_cpu_disas_set_info;
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cc->tcg_initialize = avr_cpu_tcg_init;
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cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
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}
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139
target/avr/cpu.h
139
target/avr/cpu.h
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#ifndef QEMU_AVR_CPU_H
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#ifndef QEMU_AVR_CPU_H
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#define QEMU_AVR_CPU_H
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#define QEMU_AVR_CPU_H
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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#include "exec/cpu-defs.h"
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#ifdef CONFIG_USER_ONLY
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#error "AVR 8-bit does not support user mode"
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#endif
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#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
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#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
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#define CPU_RESOLVING_TYPE TYPE_AVR_CPU
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#define TCG_GUEST_DEFAULT_MO 0
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#define TCG_GUEST_DEFAULT_MO 0
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/*
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/*
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@ -63,4 +72,134 @@
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*/
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*/
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#define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS)
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#define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS)
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typedef struct CPUAVRState CPUAVRState;
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struct CPUAVRState {
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uint32_t pc_w; /* 0x003fffff up to 22 bits */
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uint32_t sregC; /* 0x00000001 1 bit */
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uint32_t sregZ; /* 0x00000001 1 bit */
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uint32_t sregN; /* 0x00000001 1 bit */
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uint32_t sregV; /* 0x00000001 1 bit */
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uint32_t sregS; /* 0x00000001 1 bit */
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uint32_t sregH; /* 0x00000001 1 bit */
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uint32_t sregT; /* 0x00000001 1 bit */
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uint32_t sregI; /* 0x00000001 1 bit */
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uint32_t rampD; /* 0x00ff0000 8 bits */
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uint32_t rampX; /* 0x00ff0000 8 bits */
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uint32_t rampY; /* 0x00ff0000 8 bits */
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uint32_t rampZ; /* 0x00ff0000 8 bits */
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uint32_t eind; /* 0x00ff0000 8 bits */
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uint32_t r[NUMBER_OF_CPU_REGISTERS]; /* 8 bits each */
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uint32_t sp; /* 16 bits */
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uint32_t skip; /* if set skip instruction */
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uint64_t intsrc; /* interrupt sources */
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bool fullacc; /* CPU/MEM if true MEM only otherwise */
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uint64_t features;
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};
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/**
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* AVRCPU:
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* @env: #CPUAVRState
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*
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* A AVR CPU.
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*/
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typedef struct AVRCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPUAVRState env;
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} AVRCPU;
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void avr_cpu_do_interrupt(CPUState *cpu);
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bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
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hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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#define cpu_list avr_cpu_list
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#define cpu_signal_handler cpu_avr_signal_handler
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#define cpu_mmu_index avr_cpu_mmu_index
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static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch)
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{
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return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
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}
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void avr_cpu_tcg_init(void);
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void avr_cpu_list(void);
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int cpu_avr_exec(CPUState *cpu);
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int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc);
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int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf,
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||||||
|
int len, bool is_write);
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||||||
|
|
||||||
|
enum {
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||||||
|
TB_FLAGS_FULL_ACCESS = 1,
|
||||||
|
TB_FLAGS_SKIP = 2,
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||||||
|
};
|
||||||
|
|
||||||
|
static inline void cpu_get_tb_cpu_state(CPUAVRState *env, target_ulong *pc,
|
||||||
|
target_ulong *cs_base, uint32_t *pflags)
|
||||||
|
{
|
||||||
|
uint32_t flags = 0;
|
||||||
|
|
||||||
|
*pc = env->pc_w * 2;
|
||||||
|
*cs_base = 0;
|
||||||
|
|
||||||
|
if (env->fullacc) {
|
||||||
|
flags |= TB_FLAGS_FULL_ACCESS;
|
||||||
|
}
|
||||||
|
if (env->skip) {
|
||||||
|
flags |= TB_FLAGS_SKIP;
|
||||||
|
}
|
||||||
|
|
||||||
|
*pflags = flags;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int cpu_interrupts_enabled(CPUAVRState *env)
|
||||||
|
{
|
||||||
|
return env->sregI != 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline uint8_t cpu_get_sreg(CPUAVRState *env)
|
||||||
|
{
|
||||||
|
uint8_t sreg;
|
||||||
|
sreg = (env->sregC) << 0
|
||||||
|
| (env->sregZ) << 1
|
||||||
|
| (env->sregN) << 2
|
||||||
|
| (env->sregV) << 3
|
||||||
|
| (env->sregS) << 4
|
||||||
|
| (env->sregH) << 5
|
||||||
|
| (env->sregT) << 6
|
||||||
|
| (env->sregI) << 7;
|
||||||
|
return sreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void cpu_set_sreg(CPUAVRState *env, uint8_t sreg)
|
||||||
|
{
|
||||||
|
env->sregC = (sreg >> 0) & 0x01;
|
||||||
|
env->sregZ = (sreg >> 1) & 0x01;
|
||||||
|
env->sregN = (sreg >> 2) & 0x01;
|
||||||
|
env->sregV = (sreg >> 3) & 0x01;
|
||||||
|
env->sregS = (sreg >> 4) & 0x01;
|
||||||
|
env->sregH = (sreg >> 5) & 0x01;
|
||||||
|
env->sregT = (sreg >> 6) & 0x01;
|
||||||
|
env->sregI = (sreg >> 7) & 0x01;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
||||||
|
MMUAccessType access_type, int mmu_idx,
|
||||||
|
bool probe, uintptr_t retaddr);
|
||||||
|
|
||||||
|
typedef CPUAVRState CPUArchState;
|
||||||
|
typedef AVRCPU ArchCPU;
|
||||||
|
|
||||||
|
#include "exec/cpu-all.h"
|
||||||
|
|
||||||
#endif /* !defined (QEMU_AVR_CPU_H) */
|
#endif /* !defined (QEMU_AVR_CPU_H) */
|
||||||
|
|
Loading…
Reference in a new issue