From 9788e8c9b64e4cebb01c96bab2b0e4c2d4454041 Mon Sep 17 00:00:00 2001 From: Aleksandar Markovic Date: Wed, 1 Jul 2020 20:25:57 +0200 Subject: [PATCH 1/3] target/mips: Remove identical if/else branches MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the segment: if (other_tc == other->current_tc) { tccause = other->CP0_Cause; } else { tccause = other->CP0_Cause; } Original contributor can't remember what was his intention. Fixes: 5a25ce9487 ("mips: Hook in more reg accesses via mttr/mftr") Buglink: https://bugs.launchpad.net/qemu/+bug/1885718 Signed-off-by: Aleksandar Markovic Message-Id: <20200701182559.28841-2-aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cp0_helper.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index bbf12e4a97..de64add038 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -375,16 +375,9 @@ target_ulong helper_mftc0_entryhi(CPUMIPSState *env) target_ulong helper_mftc0_cause(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - int32_t tccause; CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) { - tccause = other->CP0_Cause; - } else { - tccause = other->CP0_Cause; - } - - return tccause; + return other->CP0_Cause; } target_ulong helper_mftc0_status(CPUMIPSState *env) From dda97e385b2f0fa84267a497596fe79898d48123 Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Fri, 3 Jul 2020 17:15:15 +0100 Subject: [PATCH 2/3] target/mips: Fix ADD.S FPU instruction MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After merging latest QEMU upstream into our CHERI fork, I noticed that some of the FPU tests in our MIPS baremetal testsuite [*] started failing. It turns out commit 1ace099f2a accidentally changed add.s into a subtract. [*] https://github.com/CTSRD-CHERI/cheritest Fixes: 1ace099f2a ("target/mips: fpu: Demacro ADD.") Signed-off-by: Alex Richardson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200703161515.25966-1-Alexander.Richardson@cl.cam.ac.uk> Signed-off-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- target/mips/fpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 7a3a61cab3..56beda49d8 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1221,7 +1221,7 @@ uint32_t helper_float_add_s(CPUMIPSState *env, { uint32_t wt2; - wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status); + wt2 = float32_add(fst0, fst1, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return wt2; } From 15d983dee95edff1dc4c0bed71ce02fff877e766 Mon Sep 17 00:00:00 2001 From: Aleksandar Markovic Date: Wed, 1 Jul 2020 20:25:58 +0200 Subject: [PATCH 3/3] MAINTAINERS: Adjust MIPS maintainership (add Huacai Chen & Jiaxun Yang) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Huacai Chen and Jiaxun Yang step in as new energy [1]. Aurelien Jarno comment [2]: It happens that I known Huacai Chen from the time he was upstreaming the Loongson 3 support to the kernel, I have been testing and reviewing his patches. I also know Jiaxun Yang from the #debian-mips IRC channel. I know that they are both very competent and have a good knowledge of the open source world. I therefore agree that they are good additions to maintain and/or review the MIPS part of QEMU. [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg718434.html [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg718738.html Signed-off-by: Aleksandar Markovic Message-Id: <20200701182559.28841-3-aleksandar.qemu.devel@gmail.com> PMD: [Split patch, added Aurelien's comment] Signed-off-by: Philippe Mathieu-Daudé Acked-by: Jiaxun Yang Acked-by: Huacai Chen --- MAINTAINERS | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fe8139f367..cdb5c6f171 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -222,6 +222,7 @@ F: disas/microblaze.c MIPS TCG CPUs M: Aleksandar Markovic R: Aurelien Jarno +R: Jiaxun Yang R: Aleksandar Rikalo S: Maintained F: target/mips/ @@ -384,6 +385,7 @@ S: Maintained F: target/arm/kvm.c MIPS KVM CPUs +M: Huacai Chen M: Aleksandar Markovic S: Odd Fixes F: target/mips/kvm.c @@ -2743,6 +2745,8 @@ F: disas/i386.c MIPS TCG target M: Aleksandar Markovic R: Aurelien Jarno +R: Huacai Chen +R: Jiaxun Yang R: Aleksandar Rikalo S: Maintained F: tcg/mips/