target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an optional feature in ARMv8.0, and mandatory in ARMv8.5. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210216224543.16142-2-rebecca@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1206,6 +1206,7 @@ void pmu_init(ARMCPU *cpu);
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#define SCTLR_TE (1U << 30) /* AArch32 only */
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#define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
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#define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
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#define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
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#define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
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#define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
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#define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
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@ -1213,7 +1214,7 @@ void pmu_init(ARMCPU *cpu);
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#define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
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#define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
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#define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
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#define SCTLR_DSSBS (1ULL << 44) /* v8.5 */
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#define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
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#define CPTR_TCPAC (1U << 31)
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#define CPTR_TTA (1U << 20)
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@ -1250,6 +1251,7 @@ void pmu_init(ARMCPU *cpu);
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#define CPSR_IL (1U << 20)
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#define CPSR_DIT (1U << 21)
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#define CPSR_PAN (1U << 22)
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#define CPSR_SSBS (1U << 23)
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#define CPSR_J (1U << 24)
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#define CPSR_IT_0_1 (3U << 25)
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#define CPSR_Q (1U << 27)
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@ -1312,6 +1314,7 @@ void pmu_init(ARMCPU *cpu);
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#define PSTATE_A (1U << 8)
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#define PSTATE_D (1U << 9)
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#define PSTATE_BTYPE (3U << 10)
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#define PSTATE_SSBS (1U << 12)
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#define PSTATE_IL (1U << 20)
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#define PSTATE_SS (1U << 21)
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#define PSTATE_PAN (1U << 22)
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@ -3915,6 +3918,11 @@ static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
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return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
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}
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static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
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{
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return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
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}
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/*
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* 64-bit feature tests via id registers.
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*/
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@ -4169,6 +4177,11 @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
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}
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static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
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}
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/*
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* Feature tests for "does this exist in either 32-bit or 64-bit?"
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*/
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@ -4450,6 +4450,24 @@ static const ARMCPRegInfo dit_reginfo = {
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.readfn = aa64_dit_read, .writefn = aa64_dit_write
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};
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static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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return env->pstate & PSTATE_SSBS;
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}
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static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS);
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}
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static const ARMCPRegInfo ssbs_reginfo = {
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.name = "SSBS", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6,
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.type = ARM_CP_NO_RAW, .access = PL0_RW,
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.readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write
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};
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static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
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const ARMCPRegInfo *ri,
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bool isread)
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@ -8244,6 +8262,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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if (cpu_isar_feature(aa64_dit, cpu)) {
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define_one_arm_cp_reg(cpu, &dit_reginfo);
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}
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if (cpu_isar_feature(aa64_ssbs, cpu)) {
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define_one_arm_cp_reg(cpu, &ssbs_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
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define_arm_cp_regs(cpu, vhe_reginfo);
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@ -9463,6 +9484,14 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
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env->uncached_cpsr &= ~(CPSR_IL | CPSR_J);
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env->daif |= mask;
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if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) {
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if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) {
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env->uncached_cpsr |= CPSR_SSBS;
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} else {
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env->uncached_cpsr &= ~CPSR_SSBS;
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}
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}
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if (new_mode == ARM_CPU_MODE_HYP) {
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env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0;
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env->elr_el[2] = env->regs[15];
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@ -9973,6 +10002,14 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
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new_mode |= PSTATE_TCO;
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}
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if (cpu_isar_feature(aa64_ssbs, cpu)) {
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if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) {
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new_mode |= PSTATE_SSBS;
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} else {
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new_mode &= ~PSTATE_SSBS;
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}
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}
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pstate_write(env, PSTATE_DAIF | new_mode);
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env->aarch64 = 1;
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aarch64_restore_sp(env, new_el);
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@ -987,6 +987,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
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if (isar_feature_aa32_dit(id)) {
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valid |= CPSR_DIT;
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}
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if (isar_feature_aa32_ssbs(id)) {
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valid |= CPSR_SSBS;
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}
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return valid;
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}
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@ -1008,6 +1011,9 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
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if (isar_feature_aa64_dit(id)) {
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valid |= PSTATE_DIT;
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}
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if (isar_feature_aa64_ssbs(id)) {
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valid |= PSTATE_SSBS;
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}
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if (isar_feature_aa64_mte(id)) {
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valid |= PSTATE_TCO;
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}
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@ -1703,6 +1703,18 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
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tcg_temp_free_i32(t1);
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break;
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case 0x19: /* SSBS */
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if (!dc_isar_feature(aa64_ssbs, s)) {
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goto do_unallocated;
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}
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if (crm & 1) {
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set_pstate_bits(PSTATE_SSBS);
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} else {
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clear_pstate_bits(PSTATE_SSBS);
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}
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/* Don't need to rebuild hflags since SSBS is a nop */
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break;
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case 0x1a: /* DIT */
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if (!dc_isar_feature(aa64_dit, s)) {
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goto do_unallocated;
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