PPC: dbdma: Move defines into header file
We usually keep struct and constant definitions in header files. Move them there to stay consistent and to make access to fields easier. Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -54,123 +54,6 @@
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/*
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/*
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*/
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*/
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/*
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* DBDMA control/status registers. All little-endian.
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*/
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#define DBDMA_CONTROL 0x00
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#define DBDMA_STATUS 0x01
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#define DBDMA_CMDPTR_HI 0x02
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#define DBDMA_CMDPTR_LO 0x03
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#define DBDMA_INTR_SEL 0x04
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#define DBDMA_BRANCH_SEL 0x05
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#define DBDMA_WAIT_SEL 0x06
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#define DBDMA_XFER_MODE 0x07
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#define DBDMA_DATA2PTR_HI 0x08
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#define DBDMA_DATA2PTR_LO 0x09
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#define DBDMA_RES1 0x0A
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#define DBDMA_ADDRESS_HI 0x0B
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#define DBDMA_BRANCH_ADDR_HI 0x0C
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#define DBDMA_RES2 0x0D
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#define DBDMA_RES3 0x0E
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#define DBDMA_RES4 0x0F
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#define DBDMA_REGS 16
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#define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t))
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#define DBDMA_CHANNEL_SHIFT 7
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#define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT)
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#define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT)
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/* Bits in control and status registers */
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#define RUN 0x8000
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#define PAUSE 0x4000
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#define FLUSH 0x2000
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#define WAKE 0x1000
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#define DEAD 0x0800
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#define ACTIVE 0x0400
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#define BT 0x0100
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#define DEVSTAT 0x00ff
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/*
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* DBDMA command structure. These fields are all little-endian!
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*/
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typedef struct dbdma_cmd {
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uint16_t req_count; /* requested byte transfer count */
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uint16_t command; /* command word (has bit-fields) */
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uint32_t phy_addr; /* physical data address */
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uint32_t cmd_dep; /* command-dependent field */
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uint16_t res_count; /* residual count after completion */
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uint16_t xfer_status; /* transfer status */
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} dbdma_cmd;
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/* DBDMA command values in command field */
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#define COMMAND_MASK 0xf000
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#define OUTPUT_MORE 0x0000 /* transfer memory data to stream */
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#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
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#define INPUT_MORE 0x2000 /* transfer stream data to memory */
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#define INPUT_LAST 0x3000 /* ditto, expect end marker */
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#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
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#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
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#define DBDMA_NOP 0x6000 /* do nothing */
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#define DBDMA_STOP 0x7000 /* suspend processing */
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/* Key values in command field */
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#define KEY_MASK 0x0700
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#define KEY_STREAM0 0x0000 /* usual data stream */
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#define KEY_STREAM1 0x0100 /* control/status stream */
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#define KEY_STREAM2 0x0200 /* device-dependent stream */
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#define KEY_STREAM3 0x0300 /* device-dependent stream */
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#define KEY_STREAM4 0x0400 /* reserved */
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#define KEY_REGS 0x0500 /* device register space */
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#define KEY_SYSTEM 0x0600 /* system memory-mapped space */
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#define KEY_DEVICE 0x0700 /* device memory-mapped space */
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/* Interrupt control values in command field */
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#define INTR_MASK 0x0030
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#define INTR_NEVER 0x0000 /* don't interrupt */
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#define INTR_IFSET 0x0010 /* intr if condition bit is 1 */
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#define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */
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#define INTR_ALWAYS 0x0030 /* always interrupt */
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/* Branch control values in command field */
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#define BR_MASK 0x000c
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#define BR_NEVER 0x0000 /* don't branch */
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#define BR_IFSET 0x0004 /* branch if condition bit is 1 */
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#define BR_IFCLR 0x0008 /* branch if condition bit is 0 */
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#define BR_ALWAYS 0x000c /* always branch */
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/* Wait control values in command field */
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#define WAIT_MASK 0x0003
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#define WAIT_NEVER 0x0000 /* don't wait */
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#define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */
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#define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */
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#define WAIT_ALWAYS 0x0003 /* always wait */
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typedef struct DBDMA_channel {
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int channel;
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uint32_t regs[DBDMA_REGS];
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qemu_irq irq;
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DBDMA_io io;
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DBDMA_rw rw;
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DBDMA_flush flush;
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dbdma_cmd current;
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int processing;
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} DBDMA_channel;
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typedef struct {
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MemoryRegion mem;
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DBDMA_channel channels[DBDMA_CHANNELS];
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} DBDMAState;
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#ifdef DEBUG_DBDMA
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#ifdef DEBUG_DBDMA
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static void dump_dbdma_cmd(dbdma_cmd *cmd)
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static void dump_dbdma_cmd(dbdma_cmd *cmd)
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{
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{
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@ -39,6 +39,124 @@ struct DBDMA_io {
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DBDMA_end dma_end;
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DBDMA_end dma_end;
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};
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};
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/*
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* DBDMA control/status registers. All little-endian.
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*/
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#define DBDMA_CONTROL 0x00
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#define DBDMA_STATUS 0x01
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#define DBDMA_CMDPTR_HI 0x02
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#define DBDMA_CMDPTR_LO 0x03
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#define DBDMA_INTR_SEL 0x04
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#define DBDMA_BRANCH_SEL 0x05
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#define DBDMA_WAIT_SEL 0x06
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#define DBDMA_XFER_MODE 0x07
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#define DBDMA_DATA2PTR_HI 0x08
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#define DBDMA_DATA2PTR_LO 0x09
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#define DBDMA_RES1 0x0A
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#define DBDMA_ADDRESS_HI 0x0B
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#define DBDMA_BRANCH_ADDR_HI 0x0C
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#define DBDMA_RES2 0x0D
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#define DBDMA_RES3 0x0E
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#define DBDMA_RES4 0x0F
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#define DBDMA_REGS 16
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#define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t))
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#define DBDMA_CHANNEL_SHIFT 7
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#define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT)
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#define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT)
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/* Bits in control and status registers */
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#define RUN 0x8000
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#define PAUSE 0x4000
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#define FLUSH 0x2000
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#define WAKE 0x1000
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#define DEAD 0x0800
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#define ACTIVE 0x0400
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#define BT 0x0100
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#define DEVSTAT 0x00ff
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/*
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* DBDMA command structure. These fields are all little-endian!
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*/
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typedef struct dbdma_cmd {
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uint16_t req_count; /* requested byte transfer count */
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uint16_t command; /* command word (has bit-fields) */
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uint32_t phy_addr; /* physical data address */
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uint32_t cmd_dep; /* command-dependent field */
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uint16_t res_count; /* residual count after completion */
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uint16_t xfer_status; /* transfer status */
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} dbdma_cmd;
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/* DBDMA command values in command field */
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#define COMMAND_MASK 0xf000
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#define OUTPUT_MORE 0x0000 /* transfer memory data to stream */
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#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
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#define INPUT_MORE 0x2000 /* transfer stream data to memory */
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#define INPUT_LAST 0x3000 /* ditto, expect end marker */
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#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
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#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
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#define DBDMA_NOP 0x6000 /* do nothing */
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#define DBDMA_STOP 0x7000 /* suspend processing */
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/* Key values in command field */
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#define KEY_MASK 0x0700
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#define KEY_STREAM0 0x0000 /* usual data stream */
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#define KEY_STREAM1 0x0100 /* control/status stream */
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#define KEY_STREAM2 0x0200 /* device-dependent stream */
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#define KEY_STREAM3 0x0300 /* device-dependent stream */
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#define KEY_STREAM4 0x0400 /* reserved */
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#define KEY_REGS 0x0500 /* device register space */
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#define KEY_SYSTEM 0x0600 /* system memory-mapped space */
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#define KEY_DEVICE 0x0700 /* device memory-mapped space */
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/* Interrupt control values in command field */
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#define INTR_MASK 0x0030
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#define INTR_NEVER 0x0000 /* don't interrupt */
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#define INTR_IFSET 0x0010 /* intr if condition bit is 1 */
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#define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */
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#define INTR_ALWAYS 0x0030 /* always interrupt */
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/* Branch control values in command field */
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#define BR_MASK 0x000c
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#define BR_NEVER 0x0000 /* don't branch */
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#define BR_IFSET 0x0004 /* branch if condition bit is 1 */
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#define BR_IFCLR 0x0008 /* branch if condition bit is 0 */
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#define BR_ALWAYS 0x000c /* always branch */
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/* Wait control values in command field */
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#define WAIT_MASK 0x0003
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#define WAIT_NEVER 0x0000 /* don't wait */
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#define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */
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#define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */
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#define WAIT_ALWAYS 0x0003 /* always wait */
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typedef struct DBDMA_channel {
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int channel;
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uint32_t regs[DBDMA_REGS];
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qemu_irq irq;
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DBDMA_io io;
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DBDMA_rw rw;
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DBDMA_flush flush;
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dbdma_cmd current;
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int processing;
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} DBDMA_channel;
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typedef struct {
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MemoryRegion mem;
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DBDMA_channel channels[DBDMA_CHANNELS];
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} DBDMAState;
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/* Externally callable functions */
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void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
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void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
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DBDMA_rw rw, DBDMA_flush flush,
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DBDMA_rw rw, DBDMA_flush flush,
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