target-ppc: add stxvb16x instruction
stxvb16x: Store VSX Vector Byte*16 Vector (8-bit elements): +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Store results in following: Little/Big-endian Storage +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -276,6 +276,25 @@ static void gen_stxvh8x(DisasContext *ctx)
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tcg_temp_free(EA);
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}
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static void gen_stxvb16x(DisasContext *ctx)
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{
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TCGv_i64 xsh = cpu_vsrh(xS(ctx->opcode));
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TCGv_i64 xsl = cpu_vsrl(xS(ctx->opcode));
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TCGv EA;
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if (unlikely(!ctx->vsx_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ);
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tcg_gen_addi_tl(EA, EA, 8);
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tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ);
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tcg_temp_free(EA);
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}
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#define MV_VSRW(name, tcgop1, tcgop2, target, source) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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@ -18,6 +18,7 @@ GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
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GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
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GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
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GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
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GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
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