target/ppc: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128
Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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62823083b8
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f34ec0f6d7
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@ -800,7 +800,7 @@ DEF_HELPER_4(dscliq, void, env, fprp, fprp, i32)
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DEF_HELPER_1(tbegin, void, env)
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DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, env)
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#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128)
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#ifdef TARGET_PPC64
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DEF_HELPER_FLAGS_3(lq_le_parallel, TCG_CALL_NO_WG, i64, env, tl, i32)
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DEF_HELPER_FLAGS_3(lq_be_parallel, TCG_CALL_NO_WG, i64, env, tl, i32)
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DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG,
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@ -25,6 +25,7 @@
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#include "exec/cpu_ldst.h"
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#include "tcg.h"
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#include "internal.h"
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#include "qemu/atomic128.h"
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//#define DEBUG_OP
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@ -215,11 +216,15 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
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return i;
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}
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#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128)
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#ifdef TARGET_PPC64
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uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr,
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uint32_t opidx)
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{
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Int128 ret = helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC());
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Int128 ret;
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/* We will have raised EXCP_ATOMIC from the translator. */
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assert(HAVE_ATOMIC128);
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ret = helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC());
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env->retxh = int128_gethi(ret);
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return int128_getlo(ret);
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}
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@ -227,7 +232,11 @@ uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr,
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uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr,
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uint32_t opidx)
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{
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Int128 ret = helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC());
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Int128 ret;
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/* We will have raised EXCP_ATOMIC from the translator. */
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assert(HAVE_ATOMIC128);
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ret = helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC());
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env->retxh = int128_gethi(ret);
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return int128_getlo(ret);
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}
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@ -235,14 +244,22 @@ uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr,
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void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr,
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uint64_t lo, uint64_t hi, uint32_t opidx)
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{
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Int128 val = int128_make128(lo, hi);
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Int128 val;
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/* We will have raised EXCP_ATOMIC from the translator. */
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assert(HAVE_ATOMIC128);
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val = int128_make128(lo, hi);
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helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC());
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}
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void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr,
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uint64_t lo, uint64_t hi, uint32_t opidx)
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{
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Int128 val = int128_make128(lo, hi);
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Int128 val;
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/* We will have raised EXCP_ATOMIC from the translator. */
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assert(HAVE_ATOMIC128);
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val = int128_make128(lo, hi);
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helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC());
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}
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@ -252,6 +269,9 @@ uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr,
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{
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bool success = false;
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/* We will have raised EXCP_ATOMIC from the translator. */
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assert(HAVE_CMPXCHG128);
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if (likely(addr == env->reserve_addr)) {
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Int128 oldv, cmpv, newv;
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@ -271,6 +291,9 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr,
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{
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bool success = false;
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/* We will have raised EXCP_ATOMIC from the translator. */
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assert(HAVE_CMPXCHG128);
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if (likely(addr == env->reserve_addr)) {
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Int128 oldv, cmpv, newv;
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@ -33,6 +33,7 @@
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#include "trace-tcg.h"
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#include "exec/translator.h"
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#include "exec/log.h"
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#include "qemu/atomic128.h"
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#define CPU_SINGLE_STEP 0x1
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@ -2654,22 +2655,22 @@ static void gen_lq(DisasContext *ctx)
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hi = cpu_gpr[rd];
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if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
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#ifdef CONFIG_ATOMIC128
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TCGv_i32 oi = tcg_temp_new_i32();
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if (ctx->le_mode) {
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tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
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gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
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if (HAVE_ATOMIC128) {
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TCGv_i32 oi = tcg_temp_new_i32();
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if (ctx->le_mode) {
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tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
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gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
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} else {
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tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
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gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
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}
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tcg_temp_free_i32(oi);
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tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
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} else {
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tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
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gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
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/* Restart with exclusive lock. */
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gen_helper_exit_atomic(cpu_env);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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tcg_temp_free_i32(oi);
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tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
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#else
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/* Restart with exclusive lock. */
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gen_helper_exit_atomic(cpu_env);
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ctx->base.is_jmp = DISAS_NORETURN;
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#endif
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} else if (ctx->le_mode) {
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tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ);
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gen_addr_add(ctx, EA, EA, 8);
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@ -2805,21 +2806,21 @@ static void gen_std(DisasContext *ctx)
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hi = cpu_gpr[rs];
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if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
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#ifdef CONFIG_ATOMIC128
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TCGv_i32 oi = tcg_temp_new_i32();
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if (ctx->le_mode) {
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tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
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gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
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if (HAVE_ATOMIC128) {
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TCGv_i32 oi = tcg_temp_new_i32();
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if (ctx->le_mode) {
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tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
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gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
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} else {
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tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
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gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
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}
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tcg_temp_free_i32(oi);
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} else {
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tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
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gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
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/* Restart with exclusive lock. */
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gen_helper_exit_atomic(cpu_env);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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tcg_temp_free_i32(oi);
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#else
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/* Restart with exclusive lock. */
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gen_helper_exit_atomic(cpu_env);
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ctx->base.is_jmp = DISAS_NORETURN;
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#endif
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} else if (ctx->le_mode) {
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tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);
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gen_addr_add(ctx, EA, EA, 8);
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@ -3404,26 +3405,26 @@ static void gen_lqarx(DisasContext *ctx)
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hi = cpu_gpr[rd];
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if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
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#ifdef CONFIG_ATOMIC128
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TCGv_i32 oi = tcg_temp_new_i32();
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if (ctx->le_mode) {
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tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16,
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ctx->mem_idx));
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gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
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if (HAVE_ATOMIC128) {
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TCGv_i32 oi = tcg_temp_new_i32();
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if (ctx->le_mode) {
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tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16,
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ctx->mem_idx));
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gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
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} else {
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tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16,
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ctx->mem_idx));
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gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
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}
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tcg_temp_free_i32(oi);
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tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
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} else {
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tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16,
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ctx->mem_idx));
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gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
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/* Restart with exclusive lock. */
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gen_helper_exit_atomic(cpu_env);
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ctx->base.is_jmp = DISAS_NORETURN;
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tcg_temp_free(EA);
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return;
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}
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tcg_temp_free_i32(oi);
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tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
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#else
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/* Restart with exclusive lock. */
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gen_helper_exit_atomic(cpu_env);
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ctx->base.is_jmp = DISAS_NORETURN;
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tcg_temp_free(EA);
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return;
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#endif
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} else if (ctx->le_mode) {
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tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16);
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tcg_gen_mov_tl(cpu_reserve, EA);
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@ -3461,20 +3462,22 @@ static void gen_stqcx_(DisasContext *ctx)
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hi = cpu_gpr[rs];
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if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
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TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);
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#ifdef CONFIG_ATOMIC128
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if (ctx->le_mode) {
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gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi);
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if (HAVE_CMPXCHG128) {
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TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);
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if (ctx->le_mode) {
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gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,
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EA, lo, hi, oi);
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} else {
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gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env,
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EA, lo, hi, oi);
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}
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tcg_temp_free_i32(oi);
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} else {
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gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi);
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/* Restart with exclusive lock. */
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gen_helper_exit_atomic(cpu_env);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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#else
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/* Restart with exclusive lock. */
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gen_helper_exit_atomic(cpu_env);
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ctx->base.is_jmp = DISAS_NORETURN;
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#endif
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tcg_temp_free(EA);
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tcg_temp_free_i32(oi);
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} else {
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TCGLabel *lab_fail = gen_new_label();
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TCGLabel *lab_over = gen_new_label();
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