monitor: Avoid CPUState in read/write functions
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber
parent
e59d167fe4
commit
f3840919e9
56
gdbstub.c
56
gdbstub.c
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@ -533,7 +533,7 @@ static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
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#define IDX_XMM_REGS (IDX_FP_REGS + 16)
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#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
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static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
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{
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if (n < CPU_NB_REGS) {
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if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
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@ -590,7 +590,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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return 0;
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}
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static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
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static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
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{
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uint16_t selector = ldl_p(mem_buf);
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@ -615,7 +615,7 @@ static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
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return 4;
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}
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static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
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{
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uint32_t tmp;
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@ -703,7 +703,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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#define GDB_CORE_XML "power-core.xml"
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#endif
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static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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/* gprs */
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@ -740,7 +740,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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return 0;
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}
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static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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/* gprs */
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@ -801,7 +801,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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#define GET_REGA(val) GET_REGL(val)
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#endif
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static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
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{
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if (n < 8) {
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/* g0..g7 */
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@ -860,7 +860,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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return 0;
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}
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static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
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{
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#if defined(TARGET_ABI32)
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abi_ulong tmp;
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@ -944,7 +944,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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#define NUM_CORE_REGS 26
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#define GDB_CORE_XML "arm-core.xml"
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static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
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{
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if (n < 16) {
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/* Core integer register. */
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@ -971,7 +971,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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return 0;
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}
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static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
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{
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uint32_t tmp;
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@ -1014,7 +1014,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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#define GDB_CORE_XML "cf-core.xml"
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static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
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{
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if (n < 8) {
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/* D0-D7 */
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@ -1033,7 +1033,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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return 0;
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}
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static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
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{
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uint32_t tmp;
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@ -1058,7 +1058,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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#define NUM_CORE_REGS 73
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static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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GET_REGL(env->active_tc.gpr[n]);
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@ -1104,7 +1104,7 @@ static unsigned int ieee_rm[] =
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#define RESTORE_ROUNDING_MODE \
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set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
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static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
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{
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target_ulong tmp;
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@ -1163,7 +1163,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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#define NUM_CORE_REGS 59
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static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
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{
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if (n < 8) {
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if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
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@ -1197,7 +1197,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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return 0;
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}
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static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
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{
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uint32_t tmp;
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@ -1244,7 +1244,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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#define NUM_CORE_REGS (32 + 5)
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static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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GET_REG32(env->regs[n]);
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@ -1254,7 +1254,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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return 0;
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}
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static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
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{
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uint32_t tmp;
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@ -1275,7 +1275,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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#define NUM_CORE_REGS 49
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static int
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read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
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read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
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{
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if (n < 15) {
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GET_REG32(env->regs[n]);
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@ -1307,7 +1307,7 @@ read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
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return 0;
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}
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static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
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{
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uint8_t srs;
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@ -1337,7 +1337,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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return 0;
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}
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static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
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{
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uint32_t tmp;
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@ -1370,7 +1370,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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#define NUM_CORE_REGS 67
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static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
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{
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uint64_t val;
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CPU_DoubleU d;
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@ -1404,7 +1404,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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GET_REGL(val);
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}
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static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
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{
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target_ulong tmp = ldtul_p(mem_buf);
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CPU_DoubleU d;
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@ -1440,7 +1440,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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#define NUM_CORE_REGS S390_NUM_TOTAL_REGS
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static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
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{
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switch (n) {
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case S390_PSWM_REGNUM: GET_REGL(env->psw.mask); break;
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@ -1464,7 +1464,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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return 0;
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}
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static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
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{
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target_ulong tmpl;
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uint32_t tmp32;
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@ -1494,7 +1494,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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#include "hw/lm32_pic.h"
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#define NUM_CORE_REGS (32 + 7)
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static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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GET_REG32(env->regs[n]);
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@ -1527,7 +1527,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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return 0;
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}
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static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
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{
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uint32_t tmp;
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@ -1573,7 +1573,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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#define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
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#define num_g_regs NUM_CORE_REGS
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static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
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{
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const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
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@ -1610,7 +1610,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
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}
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}
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static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
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static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
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{
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uint32_t tmp;
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const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
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