q35: implement 128K SMRAM at default SMBASE address
It's not what real HW does, implementing which would be overkill [**]
and would require complex cross stack changes (QEMU+firmware) to make
it work.
So considering that SMRAM is owned by MCH, for simplicity (ab)use
reserved Q35 register, which allows QEMU and firmware easily init
and make RAM at SMBASE available only from SMM context.
Patch uses commit (2f295167e0
q35/mch: implement extended TSEG sizes)
for inspiration and uses reserved register in config space at 0x9c
offset [*] to extend q35 pci-host with ability to use 128K at
0x30000 as SMRAM and hide it (like TSEG) from non-SMM context.
Usage:
1: write 0xff in the register
2: if the feature is supported, follow up read from the register
should return 0x01. At this point RAM at 0x30000 is still
available for SMI handler configuration from non-SMM context
3: writing 0x02 in the register, locks SMBASE area, making its contents
available only from SMM context. In non-SMM context, reads return
0xff and writes are ignored. Further writes into the register are
ignored until the system reset.
*) https://www.mail-archive.com/qemu-devel@nongnu.org/msg455991.html
**) https://www.mail-archive.com/qemu-devel@nongnu.org/msg646965.html
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <1575896942-331151-3-git-send-email-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
parent
3e08b2b9cb
commit
f404220e27
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@ -93,7 +93,9 @@
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#include "fw_cfg.h"
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#include "fw_cfg.h"
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#include "trace.h"
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#include "trace.h"
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GlobalProperty pc_compat_4_2[] = {};
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GlobalProperty pc_compat_4_2[] = {
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{ "mch", "smbase-smram", "off" },
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};
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const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
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const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
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GlobalProperty pc_compat_4_1[] = {};
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GlobalProperty pc_compat_4_1[] = {};
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@ -275,20 +275,20 @@ static const TypeInfo q35_host_info = {
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* MCH D0:F0
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* MCH D0:F0
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*/
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*/
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static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size)
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static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size)
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{
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{
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return 0xffffffff;
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return 0xffffffff;
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}
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}
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static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val,
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static void blackhole_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned width)
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unsigned width)
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{
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{
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/* nothing */
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/* nothing */
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}
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}
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static const MemoryRegionOps tseg_blackhole_ops = {
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static const MemoryRegionOps blackhole_ops = {
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.read = tseg_blackhole_read,
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.read = blackhole_read,
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.write = tseg_blackhole_write,
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.write = blackhole_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 1,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.valid.max_access_size = 4,
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@ -430,6 +430,46 @@ static void mch_update_ext_tseg_mbytes(MCHPCIState *mch)
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}
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}
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}
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}
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static void mch_update_smbase_smram(MCHPCIState *mch)
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{
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PCIDevice *pd = PCI_DEVICE(mch);
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uint8_t *reg = pd->config + MCH_HOST_BRIDGE_F_SMBASE;
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bool lck;
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if (!mch->has_smram_at_smbase) {
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return;
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}
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if (*reg == MCH_HOST_BRIDGE_F_SMBASE_QUERY) {
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pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] =
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MCH_HOST_BRIDGE_F_SMBASE_LCK;
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*reg = MCH_HOST_BRIDGE_F_SMBASE_IN_RAM;
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return;
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}
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/*
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* default/reset state, discard written value
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* which will disable SMRAM balackhole at SMBASE
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*/
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if (pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] == 0xff) {
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*reg = 0x00;
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}
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memory_region_transaction_begin();
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if (*reg & MCH_HOST_BRIDGE_F_SMBASE_LCK) {
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/* disable all writes */
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pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] &=
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~MCH_HOST_BRIDGE_F_SMBASE_LCK;
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*reg = MCH_HOST_BRIDGE_F_SMBASE_LCK;
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lck = true;
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} else {
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lck = false;
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}
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memory_region_set_enabled(&mch->smbase_blackhole, lck);
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memory_region_set_enabled(&mch->smbase_window, lck);
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memory_region_transaction_commit();
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}
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static void mch_write_config(PCIDevice *d,
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static void mch_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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uint32_t address, uint32_t val, int len)
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{
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{
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@ -456,6 +496,10 @@ static void mch_write_config(PCIDevice *d,
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MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) {
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MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) {
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mch_update_ext_tseg_mbytes(mch);
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mch_update_ext_tseg_mbytes(mch);
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}
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}
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if (ranges_overlap(address, len, MCH_HOST_BRIDGE_F_SMBASE, 1)) {
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mch_update_smbase_smram(mch);
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}
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}
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}
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static void mch_update(MCHPCIState *mch)
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static void mch_update(MCHPCIState *mch)
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@ -464,6 +508,7 @@ static void mch_update(MCHPCIState *mch)
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mch_update_pam(mch);
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mch_update_pam(mch);
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mch_update_smram(mch);
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mch_update_smram(mch);
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mch_update_ext_tseg_mbytes(mch);
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mch_update_ext_tseg_mbytes(mch);
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mch_update_smbase_smram(mch);
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/*
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/*
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* pci hole goes from end-of-low-ram to io-apic.
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* pci hole goes from end-of-low-ram to io-apic.
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@ -514,6 +559,9 @@ static void mch_reset(DeviceState *qdev)
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MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY);
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MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY);
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}
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}
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d->config[MCH_HOST_BRIDGE_F_SMBASE] = 0;
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d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff;
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mch_update(mch);
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mch_update(mch);
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}
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}
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@ -563,7 +611,7 @@ static void mch_realize(PCIDevice *d, Error **errp)
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memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram);
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memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram);
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memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch),
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memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch),
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&tseg_blackhole_ops, NULL,
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&blackhole_ops, NULL,
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"tseg-blackhole", 0);
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"tseg-blackhole", 0);
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memory_region_set_enabled(&mch->tseg_blackhole, false);
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memory_region_set_enabled(&mch->tseg_blackhole, false);
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memory_region_add_subregion_overlap(mch->system_memory,
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memory_region_add_subregion_overlap(mch->system_memory,
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@ -575,6 +623,27 @@ static void mch_realize(PCIDevice *d, Error **errp)
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memory_region_set_enabled(&mch->tseg_window, false);
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memory_region_set_enabled(&mch->tseg_window, false);
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memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size,
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memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size,
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&mch->tseg_window);
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&mch->tseg_window);
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/*
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* This is not what hardware does, so it's QEMU specific hack.
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* See commit message for details.
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*/
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memory_region_init_io(&mch->smbase_blackhole, OBJECT(mch), &blackhole_ops,
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NULL, "smbase-blackhole",
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MCH_HOST_BRIDGE_SMBASE_SIZE);
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memory_region_set_enabled(&mch->smbase_blackhole, false);
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memory_region_add_subregion_overlap(mch->system_memory,
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MCH_HOST_BRIDGE_SMBASE_ADDR,
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&mch->smbase_blackhole, 1);
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memory_region_init_alias(&mch->smbase_window, OBJECT(mch),
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"smbase-window", mch->ram_memory,
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MCH_HOST_BRIDGE_SMBASE_ADDR,
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MCH_HOST_BRIDGE_SMBASE_SIZE);
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memory_region_set_enabled(&mch->smbase_window, false);
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memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR,
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&mch->smbase_window);
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object_property_add_const_link(qdev_get_machine(), "smram",
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object_property_add_const_link(qdev_get_machine(), "smram",
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OBJECT(&mch->smram), &error_abort);
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OBJECT(&mch->smram), &error_abort);
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@ -601,6 +670,7 @@ uint64_t mch_mcfg_base(void)
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static Property mch_props[] = {
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static Property mch_props[] = {
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DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes,
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DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes,
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16),
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16),
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DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, true),
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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@ -32,6 +32,7 @@
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#include "hw/acpi/ich9.h"
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#include "hw/acpi/ich9.h"
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#include "hw/pci-host/pam.h"
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#include "hw/pci-host/pam.h"
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#include "hw/i386/intel_iommu.h"
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#include "hw/i386/intel_iommu.h"
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#include "qemu/units.h"
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#define TYPE_Q35_HOST_DEVICE "q35-pcihost"
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#define TYPE_Q35_HOST_DEVICE "q35-pcihost"
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#define Q35_HOST_DEVICE(obj) \
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#define Q35_HOST_DEVICE(obj) \
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@ -54,6 +55,8 @@ typedef struct MCHPCIState {
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MemoryRegion smram_region, open_high_smram;
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MemoryRegion smram_region, open_high_smram;
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MemoryRegion smram, low_smram, high_smram;
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MemoryRegion smram, low_smram, high_smram;
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MemoryRegion tseg_blackhole, tseg_window;
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MemoryRegion tseg_blackhole, tseg_window;
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MemoryRegion smbase_blackhole, smbase_window;
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bool has_smram_at_smbase;
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Range pci_hole;
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Range pci_hole;
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uint64_t below_4g_mem_size;
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uint64_t below_4g_mem_size;
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uint64_t above_4g_mem_size;
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uint64_t above_4g_mem_size;
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@ -97,6 +100,13 @@ typedef struct Q35PCIHost {
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#define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff
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#define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff
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#define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff
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#define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff
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#define MCH_HOST_BRIDGE_SMBASE_SIZE (128 * KiB)
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#define MCH_HOST_BRIDGE_SMBASE_ADDR 0x30000
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#define MCH_HOST_BRIDGE_F_SMBASE 0x9c
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#define MCH_HOST_BRIDGE_F_SMBASE_QUERY 0xff
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#define MCH_HOST_BRIDGE_F_SMBASE_IN_RAM 0x01
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#define MCH_HOST_BRIDGE_F_SMBASE_LCK 0x02
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#define MCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */
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#define MCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */
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#define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */
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#define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */
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#define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000
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#define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000
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