target/ppc: Create helper_scv
Perform the test against FSCR_SCV at runtime, in the helper. This means we can remove the incorrect set against SCV in ppc_tr_init_disas_context and do not need to add an HFLAGS bit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210323184340.619757-6-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -1130,6 +1130,15 @@ void helper_store_msr(CPUPPCState *env, target_ulong val)
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}
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#if defined(TARGET_PPC64)
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void helper_scv(CPUPPCState *env, uint32_t lev)
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{
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if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) {
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raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev);
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} else {
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raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV);
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}
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}
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void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
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{
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CPUState *cs;
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@ -13,6 +13,7 @@ DEF_HELPER_1(rfci, void, env)
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DEF_HELPER_1(rfdi, void, env)
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DEF_HELPER_1(rfmci, void, env)
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#if defined(TARGET_PPC64)
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DEF_HELPER_2(scv, noreturn, env, i32)
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DEF_HELPER_2(pminsn, void, env, i32)
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DEF_HELPER_1(rfid, void, env)
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DEF_HELPER_1(rfscv, void, env)
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@ -173,7 +173,6 @@ struct DisasContext {
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bool vsx_enabled;
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bool spe_enabled;
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bool tm_enabled;
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bool scv_enabled;
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bool gtse;
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ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
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int singlestep_enabled;
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@ -4081,15 +4080,16 @@ static void gen_sc(DisasContext *ctx)
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#if !defined(CONFIG_USER_ONLY)
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static void gen_scv(DisasContext *ctx)
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{
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uint32_t lev;
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uint32_t lev = (ctx->opcode >> 5) & 0x7F;
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if (unlikely(!ctx->scv_enabled)) {
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gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_SCV);
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return;
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/* Set the PC back to the faulting instruction. */
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if (ctx->exception == POWERPC_EXCP_NONE) {
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gen_update_nip(ctx, ctx->base.pc_next - 4);
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}
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gen_helper_scv(cpu_env, tcg_constant_i32(lev));
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lev = (ctx->opcode >> 5) & 0x7F;
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gen_exception_err(ctx, POWERPC_SYSCALL_VECTORED, lev);
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/* This need not be exact, just not POWERPC_EXCP_NONE */
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ctx->exception = POWERPC_SYSCALL_VECTORED;
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}
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#endif
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#endif
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@ -7907,12 +7907,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1;
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ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1;
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ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1;
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if ((env->flags & POWERPC_FLAG_SCV)
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&& (env->spr[SPR_FSCR] & (1ull << FSCR_SCV))) {
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ctx->scv_enabled = true;
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} else {
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ctx->scv_enabled = false;
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}
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ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
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ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
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