ppc: Properly tag the translation cache based on MMU mode
We used to always flush the TLB when changing relocation mode in MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data). We don't anymore since we have split mmu_idx for instruction and data. However, since we hard code the mmu_idx in the translated code, we now need to also make sure MSR:IR and MSR:DR are part of the hflags used to tag translated code, so that we use different translated code for different MMU settings. Darwin gets hurt by this problem. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -95,7 +95,7 @@ static inline void hreg_compute_hflags(CPUPPCState *env)
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/* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
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hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
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(1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
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(1 << MSR_LE) | (1 << MSR_VSX);
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(1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
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hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
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hreg_compute_mem_idx(env);
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env->hflags = env->msr & hflags_mask;
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