TCG host support for mips64
-----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJYcnxRAAoJEK0ScMxN0CebmQ0H/AzZvSjBBrXRrcvG/I5cpiKc 8CmFiRPuW4ZDG25VnyGfJdicqD5Cp7ezIfTJBwbVO+kD6toOgmvXQkpXUqdiu+ak Zl+yWqXoNasw5oi8Xis0LyeN+lvk8/AmahpBkiaKMm8Wzu8hZTZZ3xNuKs5Hf3oc sCjg4d1anxsQTLuxhnYZO6orrv7AzNbv2f4cvzDEe9sEB904sYJlfqQmquve4iJs RsQ4wTppcMu3tH+T8PtBZtECvBLpfwnFflIzoWzz3ni7n1CPxjoopSJxOFaCQtBW FvhfRrN9ytxNOrrSUH/9lL7lC2rdDMgX+hYzarkAbe/GUsrWkDU0KALw7ijdiRc= =fYDP -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170108' into staging TCG host support for mips64 # gpg: Signature made Sun 08 Jan 2017 17:52:17 GMT # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20170108: translate-all: Avoid -Werror=switch-bool tcg-mips: Adjust qemu_ld/st for mips64 tcg-mips: Adjust calling conventions for mips64 tcg-mips: Add tcg unwind info tcg-mips: Adjust prologue for mips64 tcg-mips: Adjust load/store functions for mips64 tcg-mips: Adjust move functions for mips64 tcg-mips: Add bswap32u and bswap64 tcg-mips: Support 64-bit opcodes tcg-mips: Add mips64 opcodes tcg-mips: Move bswap code to a subroutine Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
f634151b02
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@ -27,6 +27,14 @@
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#ifndef MIPS_TCG_TARGET_H
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#define MIPS_TCG_TARGET_H
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#if _MIPS_SIM == _ABIO32
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# define TCG_TARGET_REG_BITS 32
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#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
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# define TCG_TARGET_REG_BITS 64
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#else
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# error "Unknown ABI"
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#endif
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
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#define TCG_TARGET_NB_REGS 32
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@ -70,9 +78,13 @@ typedef enum {
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} TCGReg;
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/* used for function call generation */
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#define TCG_TARGET_STACK_ALIGN 8
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#define TCG_TARGET_CALL_STACK_OFFSET 16
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#define TCG_TARGET_CALL_ALIGN_ARGS 1
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#define TCG_TARGET_STACK_ALIGN 16
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#if _MIPS_SIM == _ABIO32
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# define TCG_TARGET_CALL_STACK_OFFSET 16
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#else
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# define TCG_TARGET_CALL_STACK_OFFSET 0
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#endif
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#define TCG_TARGET_CALL_ALIGN_ARGS 1
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/* MOVN/MOVZ instructions detection */
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#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
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@ -117,21 +129,61 @@ extern bool use_mips32r2_instructions;
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#define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions)
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#define TCG_TARGET_HAS_muluh_i32 1
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#define TCG_TARGET_HAS_mulsh_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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#define TCG_TARGET_HAS_extrl_i64_i32 1
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#define TCG_TARGET_HAS_extrh_i64_i32 1
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#define TCG_TARGET_HAS_div_i64 1
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#define TCG_TARGET_HAS_rem_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_nor_i64 1
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#define TCG_TARGET_HAS_andc_i64 0
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#define TCG_TARGET_HAS_orc_i64 0
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#define TCG_TARGET_HAS_eqv_i64 0
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#define TCG_TARGET_HAS_nand_i64 0
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#define TCG_TARGET_HAS_add2_i64 0
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#define TCG_TARGET_HAS_sub2_i64 0
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#define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions)
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#define TCG_TARGET_HAS_muls2_i64 (!use_mips32r6_instructions)
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#define TCG_TARGET_HAS_muluh_i64 1
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#define TCG_TARGET_HAS_mulsh_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext32u_i64 1
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#endif
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/* optional instructions detected at runtime */
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#define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions
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#define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_bswap32_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_movcond_i64 use_movnz_instructions
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#define TCG_TARGET_HAS_bswap16_i64 use_mips32r2_instructions
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#define TCG_TARGET_HAS_bswap32_i64 use_mips32r2_instructions
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#define TCG_TARGET_HAS_bswap64_i64 use_mips32r2_instructions
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#define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions
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#define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
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#define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
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#define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions
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#endif
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/* optional instructions automatically implemented */
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#define TCG_TARGET_HAS_neg_i32 0 /* sub rd, zero, rt */
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#define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
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#define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_neg_i64 0 /* sub rd, zero, rt */
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#define TCG_TARGET_HAS_ext8u_i64 0 /* andi rt, rs, 0xff */
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#define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */
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#endif
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#ifdef __OpenBSD__
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#include <machine/sysarch.h>
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#else
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File diff suppressed because it is too large
Load diff
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@ -753,7 +753,7 @@ static inline void *alloc_code_gen_buffer(void)
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size_t size2;
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void *buf2 = mmap(NULL, size + qemu_real_host_page_size,
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PROT_NONE, flags, -1, 0);
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switch (buf2 != MAP_FAILED) {
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switch ((int)(buf2 != MAP_FAILED)) {
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case 1:
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if (!cross_256mb(buf2, size)) {
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/* Success! Use the new buffer. */
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