target/arm: make ARMCPU.clidr 64-bit
The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit 32, as well as adding a Ttype<n> field when FEAT_MTE is implemented. Extend the clidr field to be able to hold this context. Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20210108185154.8108-3-leif@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -938,7 +938,7 @@ struct ARMCPU {
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uint32_t id_afr0;
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uint32_t id_afr0;
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uint64_t id_aa64afr0;
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uint64_t id_aa64afr0;
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uint64_t id_aa64afr1;
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uint64_t id_aa64afr1;
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uint32_t clidr;
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uint64_t clidr;
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uint64_t mp_affinity; /* MP ID without feature bits */
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uint64_t mp_affinity; /* MP ID without feature bits */
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/* The elements of this array are the CCSIDR values for each cache,
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/* The elements of this array are the CCSIDR values for each cache,
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* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
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* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
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