From f66a0ecf233cae4cf170ccd1c339776b5b344775 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Mon, 18 Feb 2019 13:27:01 +0100 Subject: [PATCH] s390x/tcg: Refactor SET FPC AND SIGNAL handling We can directly work on the uint64_t value, no need for a temporary uint32_t value. Also cleanup and shorten the comments. Reviewed-by: Richard Henderson Signed-off-by: David Hildenbrand Message-Id: <20190218122710.23639-7-david@redhat.com> Signed-off-by: Cornelia Huck --- target/s390x/fpu_helper.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c index 64efab72a4..ea5a37ac5e 100644 --- a/target/s390x/fpu_helper.c +++ b/target/s390x/fpu_helper.c @@ -771,21 +771,23 @@ void HELPER(sfpc)(CPUS390XState *env, uint64_t fpc) } /* set fpc and signal */ -void HELPER(sfas)(CPUS390XState *env, uint64_t val) +void HELPER(sfas)(CPUS390XState *env, uint64_t fpc) { uint32_t signalling = env->fpc; - uint32_t source = val; uint32_t s390_exc; - /* The contents of the source operand are placed in the FPC register; - then the flags in the FPC register are set to the logical OR of the - signalling flags and the source flags. */ - env->fpc = source | (signalling & 0x00ff0000); - set_float_rounding_mode(fpc_to_rnd[source & 3], &env->fpu_status); + /* + * FPC is set to the FPC operand with a bitwise OR of the signalling + * flags. + */ + env->fpc = fpc | (signalling & 0x00ff0000); + set_float_rounding_mode(fpc_to_rnd[fpc & 3], &env->fpu_status); - /* If any signalling flag is 1 and the corresponding source mask - is also 1, a simulated-iee-exception trap occurs. */ - s390_exc = (signalling >> 16) & (source >> 24); + /* + * If any signaling flag is enabled in the new FPC mask, a + * simulated-iee-exception exception occurs. + */ + s390_exc = (signalling >> 16) & (fpc >> 24); if (s390_exc) { tcg_s390_data_exception(env, s390_exc | 3, GETPC()); }