pci: fix bridge control bit wmask
Bits 12 to 15 in bridge control register are reserver and must be read-only zero, curent mask is 0xffff which makes them writeable. Fix this up by using symbolic bit names for writeable bits instead of a hardcoded constant. Fix a comment w1mask -> w1cmask as well. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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09b926d446
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26
hw/pci.c
26
hw/pci.c
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@ -558,7 +558,7 @@ static void pci_init_wmask(PCIDevice *dev)
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static void pci_init_w1cmask(PCIDevice *dev)
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{
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/*
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* Note: It's okay to set w1mask even for readonly bits as
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* Note: It's okay to set w1cmask even for readonly bits as
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* long as their value is hardwired to 0.
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*/
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pci_set_word(dev->w1cmask + PCI_STATUS,
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@ -588,7 +588,29 @@ static void pci_init_wmask_bridge(PCIDevice *d)
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/* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
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memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
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pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
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/* TODO: add this define to pci_regs.h in linux and then in qemu. */
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#define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
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#define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
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#define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
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#define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
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#define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
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pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
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PCI_BRIDGE_CTL_PARITY |
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PCI_BRIDGE_CTL_SERR |
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PCI_BRIDGE_CTL_ISA |
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PCI_BRIDGE_CTL_VGA |
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PCI_BRIDGE_CTL_VGA_16BIT |
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PCI_BRIDGE_CTL_MASTER_ABORT |
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PCI_BRIDGE_CTL_BUS_RESET |
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PCI_BRIDGE_CTL_FAST_BACK |
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PCI_BRIDGE_CTL_DISCARD |
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PCI_BRIDGE_CTL_SEC_DISCARD |
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PCI_BRIDGE_CTL_DISCARD_STATUS |
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PCI_BRIDGE_CTL_DISCARD_SERR);
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/* Below does not do anything as we never set this bit, put here for
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* completeness. */
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pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
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PCI_BRIDGE_CTL_DISCARD_STATUS);
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}
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static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
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