armv7m: Rename nvic_state to NVICState
Rename the nvic_state struct to NVICState, to match our naming conventions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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c98c9eba88
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f797c07507
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@ -21,7 +21,7 @@
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#include "gic_internal.h"
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#include "gic_internal.h"
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#include "qemu/log.h"
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#include "qemu/log.h"
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typedef struct {
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typedef struct NVICState {
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GICState gic;
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GICState gic;
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ARMCPU *cpu;
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ARMCPU *cpu;
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struct {
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struct {
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@ -35,7 +35,7 @@ typedef struct {
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MemoryRegion container;
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MemoryRegion container;
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uint32_t num_irq;
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uint32_t num_irq;
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qemu_irq sysresetreq;
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qemu_irq sysresetreq;
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} nvic_state;
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} NVICState;
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#define TYPE_NVIC "armv7m_nvic"
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#define TYPE_NVIC "armv7m_nvic"
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/**
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/**
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@ -57,7 +57,7 @@ typedef struct NVICClass {
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#define NVIC_GET_CLASS(obj) \
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#define NVIC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(NVICClass, (obj), TYPE_NVIC)
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OBJECT_GET_CLASS(NVICClass, (obj), TYPE_NVIC)
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#define NVIC(obj) \
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#define NVIC(obj) \
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OBJECT_CHECK(nvic_state, (obj), TYPE_NVIC)
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OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
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static const uint8_t nvic_id[] = {
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static const uint8_t nvic_id[] = {
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0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
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0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
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@ -74,7 +74,7 @@ static const uint8_t nvic_id[] = {
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int system_clock_scale;
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int system_clock_scale;
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/* Conversion factor from qemu timer to SysTick frequencies. */
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/* Conversion factor from qemu timer to SysTick frequencies. */
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static inline int64_t systick_scale(nvic_state *s)
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static inline int64_t systick_scale(NVICState *s)
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{
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{
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if (s->systick.control & SYSTICK_CLKSOURCE)
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if (s->systick.control & SYSTICK_CLKSOURCE)
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return system_clock_scale;
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return system_clock_scale;
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@ -82,7 +82,7 @@ static inline int64_t systick_scale(nvic_state *s)
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return 1000;
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return 1000;
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}
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}
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static void systick_reload(nvic_state *s, int reset)
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static void systick_reload(NVICState *s, int reset)
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{
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{
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/* The Cortex-M3 Devices Generic User Guide says that "When the
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/* The Cortex-M3 Devices Generic User Guide says that "When the
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* ENABLE bit is set to 1, the counter loads the RELOAD value from the
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* ENABLE bit is set to 1, the counter loads the RELOAD value from the
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@ -101,7 +101,7 @@ static void systick_reload(nvic_state *s, int reset)
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static void systick_timer_tick(void * opaque)
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static void systick_timer_tick(void * opaque)
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{
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{
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nvic_state *s = (nvic_state *)opaque;
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NVICState *s = (NVICState *)opaque;
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s->systick.control |= SYSTICK_COUNTFLAG;
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s->systick.control |= SYSTICK_COUNTFLAG;
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if (s->systick.control & SYSTICK_TICKINT) {
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if (s->systick.control & SYSTICK_TICKINT) {
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/* Trigger the interrupt. */
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/* Trigger the interrupt. */
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@ -114,7 +114,7 @@ static void systick_timer_tick(void * opaque)
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}
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}
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}
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}
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static void systick_reset(nvic_state *s)
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static void systick_reset(NVICState *s)
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{
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{
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s->systick.control = 0;
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s->systick.control = 0;
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s->systick.reload = 0;
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s->systick.reload = 0;
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@ -126,7 +126,7 @@ static void systick_reset(nvic_state *s)
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IRQ is #16. The internal GIC routines use #32 as the first IRQ. */
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IRQ is #16. The internal GIC routines use #32 as the first IRQ. */
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void armv7m_nvic_set_pending(void *opaque, int irq)
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void armv7m_nvic_set_pending(void *opaque, int irq)
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{
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{
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nvic_state *s = (nvic_state *)opaque;
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NVICState *s = (NVICState *)opaque;
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if (irq >= 16)
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if (irq >= 16)
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irq += 16;
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irq += 16;
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gic_set_pending_private(&s->gic, 0, irq);
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gic_set_pending_private(&s->gic, 0, irq);
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@ -135,7 +135,7 @@ void armv7m_nvic_set_pending(void *opaque, int irq)
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/* Make pending IRQ active. */
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/* Make pending IRQ active. */
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int armv7m_nvic_acknowledge_irq(void *opaque)
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int armv7m_nvic_acknowledge_irq(void *opaque)
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{
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{
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nvic_state *s = (nvic_state *)opaque;
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NVICState *s = (NVICState *)opaque;
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uint32_t irq;
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uint32_t irq;
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irq = gic_acknowledge_irq(&s->gic, 0, MEMTXATTRS_UNSPECIFIED);
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irq = gic_acknowledge_irq(&s->gic, 0, MEMTXATTRS_UNSPECIFIED);
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@ -148,13 +148,13 @@ int armv7m_nvic_acknowledge_irq(void *opaque)
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void armv7m_nvic_complete_irq(void *opaque, int irq)
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void armv7m_nvic_complete_irq(void *opaque, int irq)
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{
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{
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nvic_state *s = (nvic_state *)opaque;
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NVICState *s = (NVICState *)opaque;
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if (irq >= 16)
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if (irq >= 16)
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irq += 16;
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irq += 16;
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gic_complete_irq(&s->gic, 0, irq, MEMTXATTRS_UNSPECIFIED);
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gic_complete_irq(&s->gic, 0, irq, MEMTXATTRS_UNSPECIFIED);
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}
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}
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static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
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static uint32_t nvic_readl(NVICState *s, uint32_t offset)
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{
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{
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ARMCPU *cpu = s->cpu;
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ARMCPU *cpu = s->cpu;
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uint32_t val;
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uint32_t val;
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@ -294,7 +294,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
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}
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}
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}
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}
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static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value)
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static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
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{
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{
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ARMCPU *cpu = s->cpu;
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ARMCPU *cpu = s->cpu;
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uint32_t oldval;
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uint32_t oldval;
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@ -425,7 +425,7 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value)
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static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
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static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
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unsigned size)
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unsigned size)
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{
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{
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nvic_state *s = (nvic_state *)opaque;
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NVICState *s = (NVICState *)opaque;
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uint32_t offset = addr;
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uint32_t offset = addr;
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int i;
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int i;
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uint32_t val;
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uint32_t val;
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@ -454,7 +454,7 @@ static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
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static void nvic_sysreg_write(void *opaque, hwaddr addr,
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static void nvic_sysreg_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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uint64_t value, unsigned size)
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{
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{
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nvic_state *s = (nvic_state *)opaque;
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NVICState *s = (NVICState *)opaque;
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uint32_t offset = addr;
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uint32_t offset = addr;
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int i;
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int i;
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@ -486,17 +486,17 @@ static const VMStateDescription vmstate_nvic = {
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.version_id = 1,
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(systick.control, nvic_state),
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VMSTATE_UINT32(systick.control, NVICState),
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VMSTATE_UINT32(systick.reload, nvic_state),
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VMSTATE_UINT32(systick.reload, NVICState),
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VMSTATE_INT64(systick.tick, nvic_state),
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VMSTATE_INT64(systick.tick, NVICState),
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VMSTATE_TIMER_PTR(systick.timer, nvic_state),
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VMSTATE_TIMER_PTR(systick.timer, NVICState),
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VMSTATE_END_OF_LIST()
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VMSTATE_END_OF_LIST()
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}
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}
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};
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};
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static void armv7m_nvic_reset(DeviceState *dev)
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static void armv7m_nvic_reset(DeviceState *dev)
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{
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{
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nvic_state *s = NVIC(dev);
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NVICState *s = NVIC(dev);
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NVICClass *nc = NVIC_GET_CLASS(s);
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NVICClass *nc = NVIC_GET_CLASS(s);
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nc->parent_reset(dev);
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nc->parent_reset(dev);
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/* Common GIC reset resets to disabled; the NVIC doesn't have
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/* Common GIC reset resets to disabled; the NVIC doesn't have
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@ -513,7 +513,7 @@ static void armv7m_nvic_reset(DeviceState *dev)
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static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
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static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
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{
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{
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nvic_state *s = NVIC(dev);
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NVICState *s = NVIC(dev);
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NVICClass *nc = NVIC_GET_CLASS(s);
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NVICClass *nc = NVIC_GET_CLASS(s);
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Error *local_err = NULL;
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Error *local_err = NULL;
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@ -569,7 +569,7 @@ static void armv7m_nvic_instance_init(Object *obj)
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*/
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*/
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GICState *s = ARM_GIC_COMMON(obj);
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GICState *s = ARM_GIC_COMMON(obj);
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DeviceState *dev = DEVICE(obj);
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DeviceState *dev = DEVICE(obj);
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nvic_state *nvic = NVIC(obj);
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NVICState *nvic = NVIC(obj);
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/* The ARM v7m may have anything from 0 to 496 external interrupt
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/* The ARM v7m may have anything from 0 to 496 external interrupt
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* IRQ lines. We default to 64. Other boards may differ and should
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* IRQ lines. We default to 64. Other boards may differ and should
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* set the num-irq property appropriately.
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* set the num-irq property appropriately.
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@ -594,7 +594,7 @@ static const TypeInfo armv7m_nvic_info = {
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.name = TYPE_NVIC,
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.name = TYPE_NVIC,
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.parent = TYPE_ARM_GIC_COMMON,
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.parent = TYPE_ARM_GIC_COMMON,
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.instance_init = armv7m_nvic_instance_init,
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.instance_init = armv7m_nvic_instance_init,
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.instance_size = sizeof(nvic_state),
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.instance_size = sizeof(NVICState),
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.class_init = armv7m_nvic_class_init,
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.class_init = armv7m_nvic_class_init,
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.class_size = sizeof(NVICClass),
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.class_size = sizeof(NVICClass),
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};
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};
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