hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board
The AN505 and AN511 happen to share the same OSCCLK values, but the AN524 will have a different set (and more of them), so split the settings out to be per-board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-5-peter.maydell@linaro.org
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@ -77,6 +77,8 @@ struct MPS2TZMachineClass {
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MPS2TZFPGAType fpga_type;
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MPS2TZFPGAType fpga_type;
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uint32_t scc_id;
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uint32_t scc_id;
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uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */
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uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */
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uint32_t len_oscclk;
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const uint32_t *oscclk;
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const char *armsse_type;
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const char *armsse_type;
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};
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};
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@ -115,6 +117,12 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
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/* Slow 32Khz S32KCLK frequency in Hz */
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/* Slow 32Khz S32KCLK frequency in Hz */
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#define S32KCLK_FRQ (32 * 1000)
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#define S32KCLK_FRQ (32 * 1000)
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static const uint32_t an505_oscclk[] = {
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40000000,
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24580000,
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25000000,
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};
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/* Create an alias of an entire original MemoryRegion @orig
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/* Create an alias of an entire original MemoryRegion @orig
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* located at @base in the memory map.
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* located at @base in the memory map.
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*/
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*/
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@ -213,17 +221,18 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
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MPS2SCC *scc = opaque;
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MPS2SCC *scc = opaque;
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DeviceState *sccdev;
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DeviceState *sccdev;
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MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
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MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
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uint32_t i;
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object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC);
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object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC);
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sccdev = DEVICE(scc);
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sccdev = DEVICE(scc);
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qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
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qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
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qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
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qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
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qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
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qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
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/* This will need to be per-FPGA image eventually */
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qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk);
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qdev_prop_set_uint32(sccdev, "len-oscclk", 3);
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for (i = 0; i < mmc->len_oscclk; i++) {
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qdev_prop_set_uint32(sccdev, "oscclk[0]", 40000000);
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g_autofree char *propname = g_strdup_printf("oscclk[%u]", i);
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qdev_prop_set_uint32(sccdev, "oscclk[1]", 24580000);
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qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]);
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qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000);
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}
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sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal);
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sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal);
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return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
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return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
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}
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}
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@ -676,6 +685,8 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
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mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
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mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
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mmc->scc_id = 0x41045050;
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mmc->scc_id = 0x41045050;
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mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
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mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
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mmc->oscclk = an505_oscclk;
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mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
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mmc->armsse_type = TYPE_IOTKIT;
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mmc->armsse_type = TYPE_IOTKIT;
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}
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}
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@ -692,6 +703,8 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
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mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
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mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
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mmc->scc_id = 0x41045210;
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mmc->scc_id = 0x41045210;
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mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
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mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
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mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */
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mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
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mmc->armsse_type = TYPE_SSE200;
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mmc->armsse_type = TYPE_SSE200;
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}
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}
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