64bit MIPS FPUs have 32 registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2610 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -62,9 +62,8 @@ struct CPUMIPSState {
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target_ulong t2;
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target_ulong t2;
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#endif
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#endif
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target_ulong HI, LO;
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target_ulong HI, LO;
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uint32_t DCR; /* ? */
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/* Floating point registers */
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/* Floating point registers */
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fpr_t fpr[16];
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fpr_t fpr[32];
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#define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2])
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#define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2])
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#define FPR_FD(cpu, n) (FPR(cpu, n)->fd)
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#define FPR_FD(cpu, n) (FPR(cpu, n)->fd)
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#define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX])
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#define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX])
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