target/ppc: Use atomic store for STQ
Section 1.4 of the Power ISA v3.0B states that this insn is single-copy atomic. As we cannot (yet) issue 128-bit stores within TCG, use the generic helpers provided. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -803,4 +803,8 @@ DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, env)
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#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128)
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DEF_HELPER_FLAGS_3(lq_le_parallel, TCG_CALL_NO_WG, i64, env, tl, i32)
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DEF_HELPER_FLAGS_3(lq_be_parallel, TCG_CALL_NO_WG, i64, env, tl, i32)
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DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG,
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void, env, tl, i64, i64, i32)
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DEF_HELPER_FLAGS_5(stq_be_parallel, TCG_CALL_NO_WG,
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void, env, tl, i64, i64, i32)
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#endif
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@ -231,6 +231,20 @@ uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr,
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env->retxh = int128_gethi(ret);
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return int128_getlo(ret);
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}
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void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr,
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uint64_t lo, uint64_t hi, uint32_t opidx)
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{
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Int128 val = int128_make128(lo, hi);
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helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC());
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}
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void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr,
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uint64_t lo, uint64_t hi, uint32_t opidx)
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{
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Int128 val = int128_make128(lo, hi);
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helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC());
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}
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#endif
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/*****************************************************************************/
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@ -2760,6 +2760,7 @@ static void gen_std(DisasContext *ctx)
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if ((ctx->opcode & 0x3) == 0x2) { /* stq */
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bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
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bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
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TCGv hi, lo;
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if (!(ctx->insns_flags & PPC_64BX)) {
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
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@ -2783,20 +2784,38 @@ static void gen_std(DisasContext *ctx)
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EA = tcg_temp_new();
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gen_addr_imm_index(ctx, EA, 0x03);
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/* We only need to swap high and low halves. gen_qemu_st64_i64 does
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necessary 64-bit byteswap already. */
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if (unlikely(ctx->le_mode)) {
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gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
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/* Note that the low part is always in RS+1, even in LE mode. */
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lo = cpu_gpr[rs + 1];
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hi = cpu_gpr[rs];
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if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
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#ifdef CONFIG_ATOMIC128
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TCGv_i32 oi = tcg_temp_new_i32();
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if (ctx->le_mode) {
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tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
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gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
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} else {
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tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
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gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
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}
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tcg_temp_free_i32(oi);
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#else
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/* Restart with exclusive lock. */
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gen_helper_exit_atomic(cpu_env);
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ctx->base.is_jmp = DISAS_NORETURN;
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#endif
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} else if (ctx->le_mode) {
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tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);
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gen_addr_add(ctx, EA, EA, 8);
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gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
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tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ);
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} else {
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gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
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tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ);
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gen_addr_add(ctx, EA, EA, 8);
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gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
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tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ);
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}
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tcg_temp_free(EA);
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} else {
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/* std / stdu*/
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/* std / stdu */
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if (Rc(ctx->opcode)) {
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if (unlikely(rA(ctx->opcode) == 0)) {
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
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