aspeed: Register all watchdogs
The ast2400 contains two and the ast2500 contains three watchdogs. Add this information to the AspeedSoCInfo and realise the correct number of watchdogs for that each SoC type. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -62,6 +62,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
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.spi_bases = aspeed_soc_ast2400_spi_bases,
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.spi_bases = aspeed_soc_ast2400_spi_bases,
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.fmc_typename = "aspeed.smc.fmc",
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.fmc_typename = "aspeed.smc.fmc",
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.spi_typename = aspeed_soc_ast2400_typenames,
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.spi_typename = aspeed_soc_ast2400_typenames,
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.wdts_num = 2,
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}, {
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}, {
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.name = "ast2400-a1",
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.name = "ast2400-a1",
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.cpu_model = "arm926",
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.cpu_model = "arm926",
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@ -72,6 +73,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
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.spi_bases = aspeed_soc_ast2400_spi_bases,
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.spi_bases = aspeed_soc_ast2400_spi_bases,
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.fmc_typename = "aspeed.smc.fmc",
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.fmc_typename = "aspeed.smc.fmc",
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.spi_typename = aspeed_soc_ast2400_typenames,
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.spi_typename = aspeed_soc_ast2400_typenames,
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.wdts_num = 2,
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}, {
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}, {
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.name = "ast2400",
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.name = "ast2400",
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.cpu_model = "arm926",
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.cpu_model = "arm926",
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@ -82,6 +84,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
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.spi_bases = aspeed_soc_ast2400_spi_bases,
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.spi_bases = aspeed_soc_ast2400_spi_bases,
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.fmc_typename = "aspeed.smc.fmc",
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.fmc_typename = "aspeed.smc.fmc",
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.spi_typename = aspeed_soc_ast2400_typenames,
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.spi_typename = aspeed_soc_ast2400_typenames,
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.wdts_num = 2,
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}, {
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}, {
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.name = "ast2500-a1",
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.name = "ast2500-a1",
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.cpu_model = "arm1176",
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.cpu_model = "arm1176",
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@ -92,6 +95,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
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.spi_bases = aspeed_soc_ast2500_spi_bases,
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.spi_bases = aspeed_soc_ast2500_spi_bases,
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.fmc_typename = "aspeed.smc.ast2500-fmc",
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.fmc_typename = "aspeed.smc.ast2500-fmc",
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.spi_typename = aspeed_soc_ast2500_typenames,
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.spi_typename = aspeed_soc_ast2500_typenames,
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.wdts_num = 3,
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},
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},
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};
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};
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@ -175,9 +179,11 @@ static void aspeed_soc_init(Object *obj)
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object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
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object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
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"ram-size", &error_abort);
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"ram-size", &error_abort);
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object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);
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for (i = 0; i < sc->info->wdts_num; i++) {
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object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);
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object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
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qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
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object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL);
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qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default());
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}
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object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100);
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object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100);
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object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL);
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object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL);
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@ -300,12 +306,15 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
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/* Watch dog */
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/* Watch dog */
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object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
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for (i = 0; i < sc->info->wdts_num; i++) {
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if (err) {
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object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
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error_propagate(errp, err);
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if (err) {
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return;
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
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ASPEED_SOC_WDT_BASE + i * 0x20);
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}
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);
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/* Net */
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/* Net */
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qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
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qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
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@ -23,6 +23,7 @@
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#include "hw/net/ftgmac100.h"
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#include "hw/net/ftgmac100.h"
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#define ASPEED_SPIS_NUM 2
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#define ASPEED_SPIS_NUM 2
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#define ASPEED_WDTS_NUM 3
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typedef struct AspeedSoCState {
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typedef struct AspeedSoCState {
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/*< private >*/
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/*< private >*/
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@ -39,7 +40,7 @@ typedef struct AspeedSoCState {
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AspeedSMCState fmc;
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AspeedSMCState fmc;
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AspeedSMCState spi[ASPEED_SPIS_NUM];
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AspeedSMCState spi[ASPEED_SPIS_NUM];
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AspeedSDMCState sdmc;
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AspeedSDMCState sdmc;
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AspeedWDTState wdt;
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AspeedWDTState wdt[ASPEED_WDTS_NUM];
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FTGMAC100State ftgmac100;
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FTGMAC100State ftgmac100;
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} AspeedSoCState;
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} AspeedSoCState;
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@ -56,6 +57,7 @@ typedef struct AspeedSoCInfo {
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const hwaddr *spi_bases;
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const hwaddr *spi_bases;
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const char *fmc_typename;
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const char *fmc_typename;
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const char **spi_typename;
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const char **spi_typename;
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int wdts_num;
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} AspeedSoCInfo;
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} AspeedSoCInfo;
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typedef struct AspeedSoCClass {
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typedef struct AspeedSoCClass {
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