pci: interrupt status bit implementation
interrupt status is a mandatory feature in PCI spec, so devices must implement it to be spec compliant. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Isaku Yamahata <yamahata@valinux.co.jp>
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hw/pci.c
26
hw/pci.c
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@ -128,11 +128,23 @@ static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
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bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
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}
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/* Update interrupt status bit in config space on interrupt
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* state change. */
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static void pci_update_irq_status(PCIDevice *dev)
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{
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if (dev->irq_state) {
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dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
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} else {
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dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
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}
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}
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static void pci_device_reset(PCIDevice *dev)
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{
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int r;
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dev->irq_state = 0;
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pci_update_irq_status(dev);
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dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER);
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dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
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@ -377,12 +389,23 @@ static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
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void pci_device_save(PCIDevice *s, QEMUFile *f)
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{
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/* Clear interrupt status bit: it is implicit
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* in irq_state which we are saving.
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* This makes us compatible with old devices
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* which never set or clear this bit. */
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s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
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vmstate_save_state(f, pci_get_vmstate(s), s);
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/* Restore the interrupt status bit. */
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pci_update_irq_status(s);
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}
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int pci_device_load(PCIDevice *s, QEMUFile *f)
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{
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return vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
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int ret;
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ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
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/* Restore the interrupt status bit. */
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pci_update_irq_status(s);
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return ret;
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}
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static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
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@ -955,6 +978,7 @@ static void pci_set_irq(void *opaque, int irq_num, int level)
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return;
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pci_set_irq_state(pci_dev, irq_num, level);
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pci_update_irq_status(pci_dev);
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pci_change_irq_level(pci_dev, irq_num, change);
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}
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1
hw/pci.h
1
hw/pci.h
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@ -102,6 +102,7 @@ typedef struct PCIIORegion {
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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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#define PCI_COMMAND_MASTER 0x4 /* Enable bus master */
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#define PCI_STATUS 0x06 /* 16 bits */
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#define PCI_STATUS_INTERRUPT 0x08
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#define PCI_REVISION_ID 0x08 /* 8 bits */
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#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
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#define PCI_CLASS_DEVICE 0x0a /* Device class */
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