target/mips: Increase 'supported ISAs/ASEs' flag holder size
Increase the size of insn_flags holder size to 64 bits. This is needed for future extensions since existing bits are almost all used. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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@ -811,7 +811,7 @@ struct CPUMIPSState {
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int CCRes; /* Cycle count resolution/divisor */
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int CCRes; /* Cycle count resolution/divisor */
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uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
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uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
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uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
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uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
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int insn_flags; /* Supported instruction set */
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uint64_t insn_flags; /* Supported instruction set */
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/* Fields up to this point are cleared by a CPU reset */
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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struct {} end_reset_fields;
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@ -59,7 +59,7 @@ struct mips_def_t {
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int32_t CP0_PageGrain_rw_bitmask;
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int32_t CP0_PageGrain_rw_bitmask;
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int32_t CP0_PageGrain;
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int32_t CP0_PageGrain;
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target_ulong CP0_EBaseWG_rw_bitmask;
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target_ulong CP0_EBaseWG_rw_bitmask;
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int insn_flags;
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uint64_t insn_flags;
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enum mips_mmu_types mmu_type;
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enum mips_mmu_types mmu_type;
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};
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};
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@ -1986,7 +1986,7 @@ typedef struct DisasContext {
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target_ulong saved_pc;
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target_ulong saved_pc;
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target_ulong page_start;
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target_ulong page_start;
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uint32_t opcode;
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uint32_t opcode;
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int insn_flags;
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uint64_t insn_flags;
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int32_t CP0_Config1;
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int32_t CP0_Config1;
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int32_t CP0_Config3;
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int32_t CP0_Config3;
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int32_t CP0_Config5;
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int32_t CP0_Config5;
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@ -2409,7 +2409,7 @@ static inline void check_dspr2(DisasContext *ctx)
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/* This code generates a "reserved instruction" exception if the
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/* This code generates a "reserved instruction" exception if the
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CPU does not support the instruction set corresponding to flags. */
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CPU does not support the instruction set corresponding to flags. */
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static inline void check_insn(DisasContext *ctx, int flags)
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static inline void check_insn(DisasContext *ctx, uint64_t flags)
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{
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{
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if (unlikely(!(ctx->insn_flags & flags))) {
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if (unlikely(!(ctx->insn_flags & flags))) {
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generate_exception_end(ctx, EXCP_RI);
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generate_exception_end(ctx, EXCP_RI);
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@ -2419,7 +2419,7 @@ static inline void check_insn(DisasContext *ctx, int flags)
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/* This code generates a "reserved instruction" exception if the
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/* This code generates a "reserved instruction" exception if the
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CPU has corresponding flag set which indicates that the instruction
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CPU has corresponding flag set which indicates that the instruction
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has been removed. */
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has been removed. */
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static inline void check_insn_opc_removed(DisasContext *ctx, int flags)
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static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
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{
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{
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if (unlikely(ctx->insn_flags & flags)) {
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if (unlikely(ctx->insn_flags & flags)) {
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generate_exception_end(ctx, EXCP_RI);
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generate_exception_end(ctx, EXCP_RI);
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