target-ppc: Add ISA2.06 Float to Integer Instructions
This patch adds the four floating point to integer conversion instructions introduced by Power ISA V2.06: - Floating Convert to Integer Word Unsigned (fctiwu) - Floating Convert to Integer Word Unsigned with Round Toward Zero (fctiwuz) - Floating Convert to Integer Doubleword Unsigned (fctidu) - Floating Convert to Integer Doubleword Unsigned with Round Toward Zero (fctiduz) A common macro is developed to eliminate repetitious code. Existing instructions are also refactoried to use this macro (fctiw, fctiwz, fctid, fctidz). Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -600,55 +600,41 @@ uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
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return farg1.ll;
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return farg1.ll;
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}
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}
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/* fctiw - fctiw. */
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uint64_t helper_fctiw(CPUPPCState *env, uint64_t arg)
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{
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CPU_DoubleU farg;
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farg.ll = arg;
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#define FPU_FCTI(op, cvt, nanval) \
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uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
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if (unlikely(float64_is_signaling_nan(farg.d))) {
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{ \
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/* sNaN conversion */
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CPU_DoubleU farg; \
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
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\
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POWERPC_EXCP_FP_VXCVI, 1);
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farg.ll = arg; \
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} else if (unlikely(float64_is_quiet_nan(farg.d) ||
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farg.ll = float64_to_##cvt(farg.d, &env->fp_status); \
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float64_is_infinity(farg.d))) {
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\
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/* qNan / infinity conversion */
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if (unlikely(env->fp_status.float_exception_flags)) { \
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
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if (float64_is_any_nan(arg)) { \
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} else {
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fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \
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farg.ll = float64_to_int32(farg.d, &env->fp_status);
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if (float64_is_signaling_nan(arg)) { \
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/* XXX: higher bits are not supposed to be significant.
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fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \
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* to make tests easier, return the same as a real PowerPC 750
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} \
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*/
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farg.ll = nanval; \
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farg.ll |= 0xFFF80000ULL << 32;
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} else if (env->fp_status.float_exception_flags & \
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}
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float_flag_invalid) { \
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return farg.ll;
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fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \
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} \
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helper_float_check_status(env); \
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} \
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return farg.ll; \
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}
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}
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/* fctiwz - fctiwz. */
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FPU_FCTI(fctiw, int32, 0x80000000)
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uint64_t helper_fctiwz(CPUPPCState *env, uint64_t arg)
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FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000)
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{
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FPU_FCTI(fctiwu, uint32, 0x00000000)
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CPU_DoubleU farg;
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FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000)
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#if defined(TARGET_PPC64)
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farg.ll = arg;
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FPU_FCTI(fctid, int64, 0x8000000000000000)
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FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000)
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if (unlikely(float64_is_signaling_nan(farg.d))) {
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FPU_FCTI(fctidu, uint64, 0x0000000000000000)
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/* sNaN conversion */
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FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000)
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
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#endif
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POWERPC_EXCP_FP_VXCVI, 1);
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} else if (unlikely(float64_is_quiet_nan(farg.d) ||
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float64_is_infinity(farg.d))) {
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/* qNan / infinity conversion */
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
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} else {
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farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
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/* XXX: higher bits are not supposed to be significant.
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* to make tests easier, return the same as a real PowerPC 750
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*/
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farg.ll |= 0xFFF80000ULL << 32;
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}
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return farg.ll;
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}
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#if defined(TARGET_PPC64)
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#if defined(TARGET_PPC64)
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/* fcfid - fcfid. */
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/* fcfid - fcfid. */
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@ -660,47 +646,7 @@ uint64_t helper_fcfid(CPUPPCState *env, uint64_t arg)
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return farg.ll;
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return farg.ll;
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}
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}
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/* fctid - fctid. */
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uint64_t helper_fctid(CPUPPCState *env, uint64_t arg)
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{
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CPU_DoubleU farg;
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farg.ll = arg;
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if (unlikely(float64_is_signaling_nan(farg.d))) {
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/* sNaN conversion */
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
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POWERPC_EXCP_FP_VXCVI, 1);
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} else if (unlikely(float64_is_quiet_nan(farg.d) ||
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float64_is_infinity(farg.d))) {
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/* qNan / infinity conversion */
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
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} else {
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farg.ll = float64_to_int64(farg.d, &env->fp_status);
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}
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return farg.ll;
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}
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/* fctidz - fctidz. */
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uint64_t helper_fctidz(CPUPPCState *env, uint64_t arg)
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{
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CPU_DoubleU farg;
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farg.ll = arg;
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if (unlikely(float64_is_signaling_nan(farg.d))) {
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/* sNaN conversion */
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
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POWERPC_EXCP_FP_VXCVI, 1);
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} else if (unlikely(float64_is_quiet_nan(farg.d) ||
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float64_is_infinity(farg.d))) {
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/* qNan / infinity conversion */
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
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} else {
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farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
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}
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return farg.ll;
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}
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#endif
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#endif
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@ -66,11 +66,15 @@ DEF_HELPER_4(fcmpo, void, env, i64, i64, i32)
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DEF_HELPER_4(fcmpu, void, env, i64, i64, i32)
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DEF_HELPER_4(fcmpu, void, env, i64, i64, i32)
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DEF_HELPER_2(fctiw, i64, env, i64)
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DEF_HELPER_2(fctiw, i64, env, i64)
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DEF_HELPER_2(fctiwu, i64, env, i64)
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DEF_HELPER_2(fctiwz, i64, env, i64)
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DEF_HELPER_2(fctiwz, i64, env, i64)
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DEF_HELPER_2(fctiwuz, i64, env, i64)
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#if defined(TARGET_PPC64)
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#if defined(TARGET_PPC64)
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DEF_HELPER_2(fcfid, i64, env, i64)
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DEF_HELPER_2(fcfid, i64, env, i64)
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DEF_HELPER_2(fctid, i64, env, i64)
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DEF_HELPER_2(fctid, i64, env, i64)
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DEF_HELPER_2(fctidu, i64, env, i64)
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DEF_HELPER_2(fctidz, i64, env, i64)
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DEF_HELPER_2(fctidz, i64, env, i64)
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DEF_HELPER_2(fctiduz, i64, env, i64)
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#endif
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#endif
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DEF_HELPER_2(frsp, i64, env, i64)
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DEF_HELPER_2(frsp, i64, env, i64)
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DEF_HELPER_2(frin, i64, env, i64)
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DEF_HELPER_2(frin, i64, env, i64)
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@ -2202,8 +2202,12 @@ GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
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/*** Floating-Point round & convert ***/
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/*** Floating-Point round & convert ***/
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/* fctiw */
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/* fctiw */
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GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
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GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
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/* fctiwu */
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GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
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/* fctiwz */
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/* fctiwz */
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GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
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GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
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/* fctiwuz */
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GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
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/* frsp */
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/* frsp */
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GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
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GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
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#if defined(TARGET_PPC64)
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#if defined(TARGET_PPC64)
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@ -2211,8 +2215,12 @@ GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
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GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
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GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
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/* fctid */
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/* fctid */
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GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
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GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
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/* fctidu */
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GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
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/* fctidz */
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/* fctidz */
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GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
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GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
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/* fctidu */
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GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
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#endif
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#endif
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/* frin */
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/* frin */
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@ -9843,12 +9851,16 @@ GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
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GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
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GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
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GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
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GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
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GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
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GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
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GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
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GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
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GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
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GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
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GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
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GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
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#if defined(TARGET_PPC64)
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#if defined(TARGET_PPC64)
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GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
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GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
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GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
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GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
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GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
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GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
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GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
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GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
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#endif
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#endif
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GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
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GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
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GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
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GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
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