hw/ppc/ppc405_uc.c: Avoid integer overflows
When performing clock calculations, the ppc405_uc code has several places where it multiplies together two 32-bit variables and assigns the result to a 64-bit variable. This doesn't quite do what is intended because C will compute a 32-bit multiply result. Add casts to ensure we don't truncate the result. (Spotted by Coverity, CID 1005504, 1005505.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -1881,7 +1881,7 @@ static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
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D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
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D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
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M = D0 * D1 * D2;
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VCO_out = cpc->sysclk * M;
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VCO_out = (uint64_t)cpc->sysclk * M;
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if (VCO_out < 400000000 || VCO_out > 800000000) {
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/* PLL cannot lock */
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cpc->pllmr &= ~0x80000000;
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@ -1892,7 +1892,7 @@ static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
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/* Bypass PLL */
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bypass_pll:
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M = D0;
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PLL_out = cpc->sysclk * M;
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PLL_out = (uint64_t)cpc->sysclk * M;
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}
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CPU_clk = PLL_out;
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if (cpc->cr1 & 0x00800000)
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@ -2242,7 +2242,7 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
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#ifdef DEBUG_CLOCKS_LL
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printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
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#endif
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VCO_out = cpc->sysclk * M * D;
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VCO_out = (uint64_t)cpc->sysclk * M * D;
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if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
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/* Error - unlock the PLL */
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printf("VCO out of range %" PRIu64 "\n", VCO_out);
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