tcg-mips: Convert to new_ldst
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -1165,10 +1165,11 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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}
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}
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}
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}
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp opc)
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
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{
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{
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TCGReg addr_regl, addr_regh __attribute__((unused));
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TCGReg addr_regl, addr_regh __attribute__((unused));
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TCGReg data_regl, data_regh;
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TCGReg data_regl, data_regh;
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TCGMemOp opc;
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#if defined(CONFIG_SOFTMMU)
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#if defined(CONFIG_SOFTMMU)
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tcg_insn_unit *label_ptr[2];
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tcg_insn_unit *label_ptr[2];
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int mem_index;
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int mem_index;
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@ -1179,9 +1180,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp opc)
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TCGReg base = TCG_REG_V0;
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TCGReg base = TCG_REG_V0;
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data_regl = *args++;
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data_regl = *args++;
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data_regh = ((opc & MO_SIZE) == MO_64 ? *args++ : 0);
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data_regh = (is_64 ? *args++ : 0);
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addr_regl = *args++;
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addr_regl = *args++;
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addr_regh = (TARGET_LONG_BITS == 64 ? *args++ : 0);
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addr_regh = (TARGET_LONG_BITS == 64 ? *args++ : 0);
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opc = *args++;
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#if defined(CONFIG_SOFTMMU)
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#if defined(CONFIG_SOFTMMU)
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mem_index = *args;
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mem_index = *args;
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@ -1246,10 +1248,11 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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}
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}
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}
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}
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static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp opc)
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static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
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{
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{
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TCGReg addr_regl, addr_regh __attribute__((unused));
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TCGReg addr_regl, addr_regh __attribute__((unused));
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TCGReg data_regl, data_regh, base;
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TCGReg data_regl, data_regh, base;
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TCGMemOp opc;
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#if defined(CONFIG_SOFTMMU)
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#if defined(CONFIG_SOFTMMU)
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tcg_insn_unit *label_ptr[2];
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tcg_insn_unit *label_ptr[2];
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int mem_index;
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int mem_index;
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@ -1257,9 +1260,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp opc)
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#endif
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#endif
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data_regl = *args++;
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data_regl = *args++;
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data_regh = ((opc & MO_SIZE) == MO_64 ? *args++ : 0);
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data_regh = (is_64 ? *args++ : 0);
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addr_regl = *args++;
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addr_regl = *args++;
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addr_regh = (TARGET_LONG_BITS == 64 ? *args++ : 0);
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addr_regh = (TARGET_LONG_BITS == 64 ? *args++ : 0);
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opc = *args++;
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#if defined(CONFIG_SOFTMMU)
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#if defined(CONFIG_SOFTMMU)
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mem_index = *args;
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mem_index = *args;
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@ -1543,35 +1547,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tcg_out_setcond2(s, args[5], args[0], args[1], args[2], args[3], args[4]);
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tcg_out_setcond2(s, args[5], args[0], args[1], args[2], args[3], args[4]);
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break;
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break;
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case INDEX_op_qemu_ld8u:
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case INDEX_op_qemu_ld_i32:
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tcg_out_qemu_ld(s, args, MO_UB);
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tcg_out_qemu_ld(s, args, false);
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break;
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break;
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case INDEX_op_qemu_ld8s:
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case INDEX_op_qemu_ld_i64:
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tcg_out_qemu_ld(s, args, MO_SB);
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tcg_out_qemu_ld(s, args, true);
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break;
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break;
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case INDEX_op_qemu_ld16u:
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case INDEX_op_qemu_st_i32:
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tcg_out_qemu_ld(s, args, MO_TEUW);
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tcg_out_qemu_st(s, args, false);
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break;
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break;
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case INDEX_op_qemu_ld16s:
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case INDEX_op_qemu_st_i64:
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tcg_out_qemu_ld(s, args, MO_TESW);
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tcg_out_qemu_st(s, args, true);
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break;
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case INDEX_op_qemu_ld32:
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tcg_out_qemu_ld(s, args, MO_TEUL);
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break;
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case INDEX_op_qemu_ld64:
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tcg_out_qemu_ld(s, args, MO_TEQ);
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break;
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case INDEX_op_qemu_st8:
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tcg_out_qemu_st(s, args, MO_UB);
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break;
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case INDEX_op_qemu_st16:
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tcg_out_qemu_st(s, args, MO_TEUW);
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break;
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case INDEX_op_qemu_st32:
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tcg_out_qemu_st(s, args, MO_TEUL);
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break;
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case INDEX_op_qemu_st64:
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tcg_out_qemu_st(s, args, MO_TEQ);
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break;
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break;
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case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
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case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
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@ -1638,29 +1624,15 @@ static const TCGTargetOpDef mips_op_defs[] = {
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{ INDEX_op_brcond2_i32, { "rZ", "rZ", "rZ", "rZ" } },
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{ INDEX_op_brcond2_i32, { "rZ", "rZ", "rZ", "rZ" } },
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#if TARGET_LONG_BITS == 32
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#if TARGET_LONG_BITS == 32
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{ INDEX_op_qemu_ld8u, { "L", "lZ" } },
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{ INDEX_op_qemu_ld_i32, { "L", "lZ" } },
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{ INDEX_op_qemu_ld8s, { "L", "lZ" } },
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{ INDEX_op_qemu_st_i32, { "SZ", "SZ" } },
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{ INDEX_op_qemu_ld16u, { "L", "lZ" } },
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{ INDEX_op_qemu_ld_i64, { "L", "L", "lZ" } },
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{ INDEX_op_qemu_ld16s, { "L", "lZ" } },
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{ INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ" } },
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{ INDEX_op_qemu_ld32, { "L", "lZ" } },
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{ INDEX_op_qemu_ld64, { "L", "L", "lZ" } },
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{ INDEX_op_qemu_st8, { "SZ", "SZ" } },
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{ INDEX_op_qemu_st16, { "SZ", "SZ" } },
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{ INDEX_op_qemu_st32, { "SZ", "SZ" } },
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{ INDEX_op_qemu_st64, { "SZ", "SZ", "SZ" } },
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#else
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#else
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{ INDEX_op_qemu_ld8u, { "L", "lZ", "lZ" } },
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{ INDEX_op_qemu_ld_i32, { "L", "lZ", "lZ" } },
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{ INDEX_op_qemu_ld8s, { "L", "lZ", "lZ" } },
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{ INDEX_op_qemu_st_i32, { "SZ", "SZ", "SZ" } },
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{ INDEX_op_qemu_ld16u, { "L", "lZ", "lZ" } },
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{ INDEX_op_qemu_ld_i64, { "L", "L", "lZ", "lZ" } },
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{ INDEX_op_qemu_ld16s, { "L", "lZ", "lZ" } },
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{ INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ", "SZ" } },
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{ INDEX_op_qemu_ld32, { "L", "lZ", "lZ" } },
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{ INDEX_op_qemu_ld64, { "L", "L", "lZ", "lZ" } },
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{ INDEX_op_qemu_st8, { "SZ", "SZ", "SZ" } },
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{ INDEX_op_qemu_st16, { "SZ", "SZ", "SZ" } },
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{ INDEX_op_qemu_st32, { "SZ", "SZ", "SZ" } },
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{ INDEX_op_qemu_st64, { "SZ", "SZ", "SZ", "SZ" } },
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#endif
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#endif
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{ -1 },
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{ -1 },
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};
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};
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@ -120,7 +120,7 @@ extern bool use_mips32r2_instructions;
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#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_new_ldst 0
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#define TCG_TARGET_HAS_new_ldst 1
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/* optional instructions automatically implemented */
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/* optional instructions automatically implemented */
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#define TCG_TARGET_HAS_neg_i32 0 /* sub rd, zero, rt */
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#define TCG_TARGET_HAS_neg_i32 0 /* sub rd, zero, rt */
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