eflags update
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@56 c046a42c-6fe2-441c-8c8c-71466251a162
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34
cpu-i386.h
34
cpu-i386.h
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@ -48,6 +48,7 @@
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#define R_FS 4
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#define R_FS 4
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#define R_GS 5
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#define R_GS 5
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/* eflags masks */
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#define CC_C 0x0001
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#define CC_C 0x0001
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#define CC_P 0x0004
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#define CC_P 0x0004
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#define CC_A 0x0010
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#define CC_A 0x0010
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@ -55,15 +56,17 @@
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#define CC_S 0x0080
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#define CC_S 0x0080
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#define CC_O 0x0800
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#define CC_O 0x0800
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#define TRAP_FLAG 0x0100
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#define TF_MASK 0x00000100
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#define INTERRUPT_FLAG 0x0200
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#define IF_MASK 0x00000200
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#define DIRECTION_FLAG 0x0400
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#define DF_MASK 0x00000400
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#define IOPL_FLAG_MASK 0x3000
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#define IOPL_MASK 0x00003000
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#define NESTED_FLAG 0x4000
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#define NT_MASK 0x00004000
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#define BYTE_FL 0x8000 /* Intel reserved! */
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#define RF_MASK 0x00010000
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#define RF_FLAG 0x10000
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#define VM_MASK 0x00020000
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#define VM_FLAG 0x20000
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#define AC_MASK 0x00040000
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/* AC 0x40000 */
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#define VIF_MASK 0x00080000
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#define VIP_MASK 0x00100000
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#define ID_MASK 0x00200000
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#define EXCP00_DIVZ 1
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#define EXCP00_DIVZ 1
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#define EXCP01_SSTP 2
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#define EXCP01_SSTP 2
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@ -158,7 +161,9 @@ typedef struct CPUX86State {
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/* standard registers */
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/* standard registers */
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uint32_t regs[8];
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uint32_t regs[8];
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uint32_t eip;
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uint32_t eip;
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uint32_t eflags;
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uint32_t eflags; /* eflags register. During CPU emulation, CC
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flags and DF are set to zero because they are
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store elsewhere */
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/* emulator internal eflags handling */
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/* emulator internal eflags handling */
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uint32_t cc_src;
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uint32_t cc_src;
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@ -183,13 +188,13 @@ typedef struct CPUX86State {
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SegmentDescriptorTable ldt;
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SegmentDescriptorTable ldt;
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SegmentDescriptorTable idt;
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SegmentDescriptorTable idt;
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/* various CPU modes */
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int vm86;
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/* exception/interrupt handling */
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/* exception/interrupt handling */
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jmp_buf jmp_env;
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jmp_buf jmp_env;
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int exception_index;
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int exception_index;
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int interrupt_request;
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int interrupt_request;
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/* user data */
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void *opaque;
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} CPUX86State;
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} CPUX86State;
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/* all CPU memory access use these macros */
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/* all CPU memory access use these macros */
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@ -418,7 +423,8 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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#define GEN_FLAG_CODE32_SHIFT 0
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#define GEN_FLAG_CODE32_SHIFT 0
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#define GEN_FLAG_ADDSEG_SHIFT 1
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#define GEN_FLAG_ADDSEG_SHIFT 1
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#define GEN_FLAG_SS32_SHIFT 2
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#define GEN_FLAG_SS32_SHIFT 2
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#define GEN_FLAG_ST_SHIFT 3
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#define GEN_FLAG_VM_SHIFT 3
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#define GEN_FLAG_ST_SHIFT 4
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int cpu_x86_gen_code(uint8_t *gen_code_buf, int max_code_size,
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int cpu_x86_gen_code(uint8_t *gen_code_buf, int max_code_size,
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int *gen_code_size_ptr,
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int *gen_code_size_ptr,
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11
exec-i386.c
11
exec-i386.c
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@ -330,9 +330,10 @@ int cpu_x86_exec(CPUX86State *env1)
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#endif
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#endif
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/* put eflags in CPU temporary format */
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/* put eflags in CPU temporary format */
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T0 = env->eflags;
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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op_movl_eflags_T0();
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DF = 1 - (2 * ((env->eflags >> 10) & 1));
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CC_OP = CC_OP_EFLAGS;
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CC_OP = CC_OP_EFLAGS;
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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env->interrupt_request = 0;
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env->interrupt_request = 0;
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/* prepare setjmp context for exception handling */
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/* prepare setjmp context for exception handling */
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@ -354,6 +355,7 @@ int cpu_x86_exec(CPUX86State *env1)
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(unsigned long)env->seg_cache[R_ES].base |
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(unsigned long)env->seg_cache[R_ES].base |
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(unsigned long)env->seg_cache[R_SS].base) != 0) <<
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(unsigned long)env->seg_cache[R_SS].base) != 0) <<
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GEN_FLAG_ADDSEG_SHIFT;
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GEN_FLAG_ADDSEG_SHIFT;
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flags |= (env->eflags & VM_MASK) >> (17 - GEN_FLAG_VM_SHIFT);
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cs_base = env->seg_cache[R_CS].base;
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cs_base = env->seg_cache[R_CS].base;
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pc = cs_base + env->eip;
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pc = cs_base + env->eip;
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tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
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tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
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@ -390,8 +392,7 @@ int cpu_x86_exec(CPUX86State *env1)
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ret = env->exception_index;
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ret = env->exception_index;
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/* restore flags in standard format */
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/* restore flags in standard format */
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op_movl_T0_eflags();
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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env->eflags = T0;
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/* restore global registers */
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/* restore global registers */
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#ifdef reg_EAX
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#ifdef reg_EAX
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@ -489,7 +490,7 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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/* for glibc 2.1 */
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/* for glibc 2.1 */
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#define REG_EIP EIP
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#define REG_EIP EIP
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#endif
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#endif
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pc = uc->uc_mcontext.gregs[EIP];
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pc = uc->uc_mcontext.gregs[REG_EIP];
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pold_set = &uc->uc_sigmask;
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pold_set = &uc->uc_sigmask;
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return handle_cpu_signal(pc, pold_set);
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return handle_cpu_signal(pc, pold_set);
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#else
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#else
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