AHCI: Protect cmd register
Many bits in the CMD register are supposed to be strictly read-only. We should not be deleting them on every write. As a side-effect: pay explicit attention to when a guest marks off the FIS Receive or Start bits, and disable the status bits ourselves, instead of letting them implicitly fall off. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1426283454-15590-3-git-send-email-jsnow@redhat.com
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@ -53,6 +53,8 @@ static int ahci_dma_prepare_buf(IDEDMA *dma, int is_write);
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static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes);
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static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes);
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static bool ahci_map_clb_address(AHCIDevice *ad);
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static bool ahci_map_clb_address(AHCIDevice *ad);
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static bool ahci_map_fis_address(AHCIDevice *ad);
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static bool ahci_map_fis_address(AHCIDevice *ad);
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static void ahci_unmap_clb_address(AHCIDevice *ad);
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static void ahci_unmap_fis_address(AHCIDevice *ad);
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static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
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static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
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@ -223,7 +225,9 @@ static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
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ahci_check_irq(s);
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ahci_check_irq(s);
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break;
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break;
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case PORT_CMD:
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case PORT_CMD:
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pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON);
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/* Block any Read-only fields from being set;
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* including LIST_ON and FIS_ON. */
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pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) | (val & ~PORT_CMD_RO_MASK);
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if (pr->cmd & PORT_CMD_START) {
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if (pr->cmd & PORT_CMD_START) {
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if (ahci_map_clb_address(&s->dev[port])) {
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if (ahci_map_clb_address(&s->dev[port])) {
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@ -232,6 +236,9 @@ static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
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error_report("AHCI: Failed to start DMA engine: "
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error_report("AHCI: Failed to start DMA engine: "
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"bad command list buffer address");
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"bad command list buffer address");
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}
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}
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} else if (pr->cmd & PORT_CMD_LIST_ON) {
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ahci_unmap_clb_address(&s->dev[port]);
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pr->cmd = pr->cmd & ~(PORT_CMD_LIST_ON);
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}
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}
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if (pr->cmd & PORT_CMD_FIS_RX) {
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if (pr->cmd & PORT_CMD_FIS_RX) {
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@ -241,6 +248,9 @@ static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
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error_report("AHCI: Failed to start FIS receive engine: "
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error_report("AHCI: Failed to start FIS receive engine: "
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"bad FIS receive buffer address");
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"bad FIS receive buffer address");
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}
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}
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} else if (pr->cmd & PORT_CMD_FIS_ON) {
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ahci_unmap_fis_address(&s->dev[port]);
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pr->cmd = pr->cmd & ~(PORT_CMD_FIS_ON);
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}
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}
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/* XXX usually the FIS would be pending on the bus here and
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/* XXX usually the FIS would be pending on the bus here and
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@ -575,6 +585,13 @@ static bool ahci_map_fis_address(AHCIDevice *ad)
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return ad->res_fis != NULL;
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return ad->res_fis != NULL;
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}
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}
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static void ahci_unmap_fis_address(AHCIDevice *ad)
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{
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dma_memory_unmap(ad->hba->as, ad->res_fis, 256,
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DMA_DIRECTION_FROM_DEVICE, 256);
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ad->res_fis = NULL;
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}
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static bool ahci_map_clb_address(AHCIDevice *ad)
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static bool ahci_map_clb_address(AHCIDevice *ad)
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{
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{
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AHCIPortRegs *pr = &ad->port_regs;
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AHCIPortRegs *pr = &ad->port_regs;
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@ -584,6 +601,13 @@ static bool ahci_map_clb_address(AHCIDevice *ad)
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return ad->lst != NULL;
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return ad->lst != NULL;
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}
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}
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static void ahci_unmap_clb_address(AHCIDevice *ad)
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{
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dma_memory_unmap(ad->hba->as, ad->lst, 1024,
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DMA_DIRECTION_FROM_DEVICE, 1024);
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ad->lst = NULL;
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}
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static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished)
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static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished)
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{
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{
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AHCIDevice *ad = &s->dev[port];
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AHCIDevice *ad = &s->dev[port];
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@ -132,6 +132,8 @@
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#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
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#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
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#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
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#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
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#define PORT_CMD_RO_MASK 0x007dffe0 /* Which CMD bits are read only? */
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/* ap->flags bits */
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/* ap->flags bits */
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#define AHCI_FLAG_NO_NCQ (1 << 24)
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#define AHCI_FLAG_NO_NCQ (1 << 24)
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#define AHCI_FLAG_IGN_IRQ_IF_ERR (1 << 25) /* ignore IRQ_IF_ERR */
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#define AHCI_FLAG_IGN_IRQ_IF_ERR (1 << 25) /* ignore IRQ_IF_ERR */
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