target-i386: Fill high bits of mtrr mask
Fill the bits between 51..number-of-physical-address-bits in the MTRR_PHYSMASKn variable range mtrr masks so that they're consistent in the migration stream irrespective of the physical address space of the source VM in a migration. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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@ -377,6 +377,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
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.driver = "vmxnet3",\
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.driver = "vmxnet3",\
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.property = "romfile",\
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.property = "romfile",\
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.value = "",\
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.value = "",\
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},\
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{\
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.driver = TYPE_X86_CPU,\
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.property = "fill-mtrr-mask",\
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.value = "off",\
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},
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},
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#define PC_COMPAT_2_5 \
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#define PC_COMPAT_2_5 \
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@ -3328,6 +3328,7 @@ static Property x86_cpu_properties[] = {
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DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
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DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
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DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
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DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
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DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
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DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
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DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
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DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
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DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
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DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
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DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
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DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
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DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
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@ -1198,6 +1198,9 @@ struct X86CPU {
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/* Compatibility bits for old machine types: */
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/* Compatibility bits for old machine types: */
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bool enable_cpuid_0xb;
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bool enable_cpuid_0xb;
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/* if true fill the top bits of the MTRR_PHYSMASKn variable range */
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bool fill_mtrr_mask;
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/* Number of physical address bits supported */
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/* Number of physical address bits supported */
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uint32_t phys_bits;
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uint32_t phys_bits;
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@ -1977,6 +1977,7 @@ static int kvm_get_msrs(X86CPU *cpu)
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CPUX86State *env = &cpu->env;
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CPUX86State *env = &cpu->env;
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struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
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struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
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int ret, i;
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int ret, i;
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uint64_t mtrr_top_bits;
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kvm_msr_buf_reset(cpu);
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kvm_msr_buf_reset(cpu);
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@ -2129,6 +2130,30 @@ static int kvm_get_msrs(X86CPU *cpu)
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}
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}
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assert(ret == cpu->kvm_msr_buf->nmsrs);
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assert(ret == cpu->kvm_msr_buf->nmsrs);
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/*
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* MTRR masks: Each mask consists of 5 parts
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* a 10..0: must be zero
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* b 11 : valid bit
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* c n-1.12: actual mask bits
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* d 51..n: reserved must be zero
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* e 63.52: reserved must be zero
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*
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* 'n' is the number of physical bits supported by the CPU and is
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* apparently always <= 52. We know our 'n' but don't know what
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* the destinations 'n' is; it might be smaller, in which case
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* it masks (c) on loading. It might be larger, in which case
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* we fill 'd' so that d..c is consistent irrespetive of the 'n'
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* we're migrating to.
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*/
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if (cpu->fill_mtrr_mask) {
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QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
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assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
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mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
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} else {
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mtrr_top_bits = 0;
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}
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for (i = 0; i < ret; i++) {
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for (i = 0; i < ret; i++) {
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uint32_t index = msrs[i].index;
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uint32_t index = msrs[i].index;
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switch (index) {
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switch (index) {
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@ -2327,7 +2352,8 @@ static int kvm_get_msrs(X86CPU *cpu)
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break;
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break;
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case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
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case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
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if (index & 1) {
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if (index & 1) {
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env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
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env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
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mtrr_top_bits;
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} else {
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} else {
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env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
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env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
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}
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}
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