target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0
In order to support Linux perf, which uses PMXEVTYPER register, this patch adds read/write access support for PMXEVTYPER. The access is CONSTRAINED UNPREDICTABLE when PMSELR is not 0x1f. Additionally this patch adds support for PMXEVTYPER_EL0. Signed-off-by: Wei Huang <wei@redhat.com> Message-id: 1486504171-26807-3-git-send-email-wei@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -307,7 +307,6 @@ typedef struct CPUARMState {
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uint64_t c9_pmcr; /* performance monitor control register */
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uint64_t c9_pmcnten; /* perf monitor counter enables */
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uint32_t c9_pmovsr; /* perf monitor overflow status */
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uint32_t c9_pmxevtyper; /* perf monitor event type */
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uint32_t c9_pmuserenr; /* perf monitor user enable */
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uint64_t c9_pmselr; /* perf monitor counter selection register */
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uint32_t c9_pminten; /* perf monitor interrupt enables */
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@ -1054,7 +1054,25 @@ static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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env->cp15.c9_pmxevtyper = value & 0xff;
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/* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
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* PMSELR value is equal to or greater than the number of implemented
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* counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
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*/
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if (env->cp15.c9_pmselr == 0x1f) {
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pmccfiltr_write(env, ri, value);
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}
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}
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static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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/* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
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* are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
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*/
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if (env->cp15.c9_pmselr == 0x1f) {
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return env->cp15.pmccfiltr_el0;
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} else {
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return 0;
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}
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}
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static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -1234,10 +1252,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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.fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
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.resetvalue = 0, },
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{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
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.access = PL0_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
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.accessfn = pmreg_access, .writefn = pmxevtyper_write,
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.raw_writefn = raw_write },
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.access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access,
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.writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
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{ .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
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.access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access,
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.writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
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/* Unimplemented, RAZ/WI. */
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{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
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.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
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