target-alpha: misc fixes
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5355 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
parent
f18cd2238d
commit
fe2b269a4f
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@ -25,15 +25,6 @@
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#include "host-utils.h"
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#include "host-utils.h"
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#include "op_helper.h"
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#include "op_helper.h"
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/* Debug stuff */
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void OPPROTO op_no_op (void)
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{
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#if !defined (DEBUG_OP)
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__asm__ __volatile__("nop" : : : "memory");
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#endif
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RETURN();
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}
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/* Load and stores */
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/* Load and stores */
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#define MEMSUFFIX _raw
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#define MEMSUFFIX _raw
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#include "op_mem.h"
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#include "op_mem.h"
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@ -43,5 +43,4 @@ void helper_mfpr (int iprn);
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void helper_mtpr (int iprn);
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void helper_mtpr (int iprn);
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void helper_ld_phys_to_virt (void);
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void helper_ld_phys_to_virt (void);
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void helper_st_phys_to_virt (void);
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void helper_st_phys_to_virt (void);
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void helper_tb_flush (void);
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@ -31,7 +31,6 @@
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#include "qemu-common.h"
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#include "qemu-common.h"
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#define DO_SINGLE_STEP
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#define DO_SINGLE_STEP
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#define GENERATE_NOP
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#define ALPHA_DEBUG_DISAS
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#define ALPHA_DEBUG_DISAS
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#define DO_TB_FLUSH
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#define DO_TB_FLUSH
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@ -104,13 +103,6 @@ static void alpha_translate_init(void)
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done_init = 1;
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done_init = 1;
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}
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}
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static always_inline void gen_op_nop (void)
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{
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#if defined(GENERATE_NOP)
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gen_op_no_op();
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#endif
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}
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/* Memory moves */
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/* Memory moves */
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#if defined(CONFIG_USER_ONLY)
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#if defined(CONFIG_USER_ONLY)
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#define OP_LD_TABLE(width) \
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#define OP_LD_TABLE(width) \
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@ -184,10 +176,7 @@ static always_inline void gen_load_mem_dyngen (DisasContext *ctx,
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int ra, int rb, int32_t disp16,
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int ra, int rb, int32_t disp16,
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int clear)
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int clear)
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{
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{
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if (ra == 31 && disp16 == 0) {
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if (ra != 31 || disp16 != 0) {
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/* UNOP */
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gen_op_nop();
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} else {
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if (rb != 31)
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if (rb != 31)
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tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
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tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
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else
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else
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@ -374,8 +363,7 @@ static always_inline void gen_fbcond (DisasContext *ctx,
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gen_set_label(l2);
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gen_set_label(l2);
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}
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}
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static always_inline void gen_cmov (DisasContext *ctx,
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static always_inline void gen_cmov (TCGCond inv_cond,
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TCGCond inv_cond,
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int ra, int rb, int rc,
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int ra, int rb, int rc,
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int islit, uint8_t lit, int mask)
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int islit, uint8_t lit, int mask)
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{
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{
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@ -487,7 +475,7 @@ static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
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tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 64 - ((lit & 7) * 8));
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tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 64 - ((lit & 7) * 8));
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else
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else
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tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
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tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
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} else {
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} else {
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TCGv tmp1, tmp2;
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TCGv tmp1, tmp2;
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tmp1 = tcg_temp_new(TCG_TYPE_I64);
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tmp1 = tcg_temp_new(TCG_TYPE_I64);
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tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
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tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
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@ -521,7 +509,7 @@ static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
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tcg_gen_shli_i64(tmp, tmp, 3);
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tcg_gen_shli_i64(tmp, tmp, 3);
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tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp);
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tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp);
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tcg_temp_free(tmp);
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tcg_temp_free(tmp);
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}
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}
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if (tcg_gen_ext_i64)
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if (tcg_gen_ext_i64)
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tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]);
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tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]);
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} else
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} else
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@ -529,9 +517,9 @@ static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
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}
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}
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/* Code to call arith3 helpers */
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/* Code to call arith3 helpers */
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static always_inline void gen_arith3_helper(void *helper,
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static always_inline void gen_arith3 (void *helper,
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int ra, int rb, int rc,
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int ra, int rb, int rc,
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int islit, uint8_t lit)
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int islit, uint8_t lit)
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{
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{
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if (unlikely(rc == 31))
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if (unlikely(rc == 31))
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return;
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return;
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@ -792,7 +780,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x0F:
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case 0x0F:
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/* CMPBGE */
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/* CMPBGE */
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gen_arith3_helper(helper_cmpbge, ra, rb, rc, islit, lit);
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gen_arith3(helper_cmpbge, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x12:
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case 0x12:
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/* S8ADDL */
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/* S8ADDL */
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break;
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break;
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case 0x40:
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case 0x40:
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/* ADDL/V */
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/* ADDL/V */
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gen_arith3_helper(helper_addlv, ra, rb, rc, islit, lit);
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gen_arith3(helper_addlv, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x49:
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case 0x49:
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/* SUBL/V */
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/* SUBL/V */
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gen_arith3_helper(helper_sublv, ra, rb, rc, islit, lit);
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gen_arith3(helper_sublv, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x4D:
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case 0x4D:
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/* CMPLT */
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/* CMPLT */
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break;
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break;
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case 0x60:
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case 0x60:
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/* ADDQ/V */
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/* ADDQ/V */
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gen_arith3_helper(helper_addqv, ra, rb, rc, islit, lit);
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gen_arith3(helper_addqv, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x69:
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case 0x69:
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/* SUBQ/V */
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/* SUBQ/V */
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gen_arith3_helper(helper_subqv, ra, rb, rc, islit, lit);
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gen_arith3(helper_subqv, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x6D:
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case 0x6D:
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/* CMPLE */
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/* CMPLE */
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@ -1015,11 +1003,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x14:
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case 0x14:
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/* CMOVLBS */
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/* CMOVLBS */
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gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 1);
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gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 1);
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break;
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break;
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case 0x16:
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case 0x16:
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/* CMOVLBC */
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/* CMOVLBC */
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gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 1);
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gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 1);
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break;
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break;
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case 0x20:
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case 0x20:
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/* BIS */
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/* BIS */
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@ -1027,7 +1015,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
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if (ra != 31) {
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if (ra != 31) {
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if (islit)
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if (islit)
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tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit);
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tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit);
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else
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else
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tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
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tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
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} else {
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} else {
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if (islit)
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if (islit)
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break;
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break;
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case 0x24:
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case 0x24:
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/* CMOVEQ */
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/* CMOVEQ */
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gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 0);
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gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 0);
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break;
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break;
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case 0x26:
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case 0x26:
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/* CMOVNE */
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/* CMOVNE */
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gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 0);
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gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 0);
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break;
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break;
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case 0x28:
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case 0x28:
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/* ORNOT */
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/* ORNOT */
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break;
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break;
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case 0x44:
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case 0x44:
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/* CMOVLT */
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/* CMOVLT */
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gen_cmov(ctx, TCG_COND_GE, ra, rb, rc, islit, lit, 0);
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gen_cmov(TCG_COND_GE, ra, rb, rc, islit, lit, 0);
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break;
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break;
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case 0x46:
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case 0x46:
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/* CMOVGE */
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/* CMOVGE */
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gen_cmov(ctx, TCG_COND_LT, ra, rb, rc, islit, lit, 0);
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gen_cmov(TCG_COND_LT, ra, rb, rc, islit, lit, 0);
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break;
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break;
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case 0x48:
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case 0x48:
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/* EQV */
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/* EQV */
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break;
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break;
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case 0x64:
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case 0x64:
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/* CMOVLE */
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/* CMOVLE */
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gen_cmov(ctx, TCG_COND_GT, ra, rb, rc, islit, lit, 0);
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gen_cmov(TCG_COND_GT, ra, rb, rc, islit, lit, 0);
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break;
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break;
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case 0x66:
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case 0x66:
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/* CMOVGT */
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/* CMOVGT */
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gen_cmov(ctx, TCG_COND_LE, ra, rb, rc, islit, lit, 0);
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gen_cmov(TCG_COND_LE, ra, rb, rc, islit, lit, 0);
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break;
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break;
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case 0x6C:
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case 0x6C:
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/* IMPLVER */
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/* IMPLVER */
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@ -1139,7 +1127,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
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switch (fn7) {
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switch (fn7) {
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case 0x02:
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case 0x02:
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/* MSKBL */
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/* MSKBL */
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gen_arith3_helper(helper_mskbl, ra, rb, rc, islit, lit);
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gen_arith3(helper_mskbl, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x06:
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case 0x06:
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/* EXTBL */
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/* EXTBL */
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@ -1147,11 +1135,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x0B:
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case 0x0B:
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/* INSBL */
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/* INSBL */
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gen_arith3_helper(helper_insbl, ra, rb, rc, islit, lit);
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gen_arith3(helper_insbl, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x12:
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case 0x12:
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/* MSKWL */
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/* MSKWL */
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gen_arith3_helper(helper_mskwl, ra, rb, rc, islit, lit);
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gen_arith3(helper_mskwl, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x16:
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case 0x16:
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/* EXTWL */
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/* EXTWL */
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@ -1159,11 +1147,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x1B:
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case 0x1B:
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/* INSWL */
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/* INSWL */
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gen_arith3_helper(helper_inswl, ra, rb, rc, islit, lit);
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gen_arith3(helper_inswl, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x22:
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case 0x22:
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/* MSKLL */
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/* MSKLL */
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gen_arith3_helper(helper_mskll, ra, rb, rc, islit, lit);
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gen_arith3(helper_mskll, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x26:
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case 0x26:
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/* EXTLL */
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/* EXTLL */
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@ -1171,19 +1159,19 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x2B:
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case 0x2B:
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/* INSLL */
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/* INSLL */
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gen_arith3_helper(helper_insll, ra, rb, rc, islit, lit);
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gen_arith3(helper_insll, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x30:
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case 0x30:
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/* ZAP */
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/* ZAP */
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gen_arith3_helper(helper_zap, ra, rb, rc, islit, lit);
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gen_arith3(helper_zap, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x31:
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case 0x31:
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/* ZAPNOT */
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/* ZAPNOT */
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gen_arith3_helper(helper_zapnot, ra, rb, rc, islit, lit);
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gen_arith3(helper_zapnot, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x32:
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case 0x32:
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/* MSKQL */
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/* MSKQL */
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gen_arith3_helper(helper_mskql, ra, rb, rc, islit, lit);
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gen_arith3(helper_mskql, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x34:
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case 0x34:
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/* SRL */
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/* SRL */
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@ -1223,7 +1211,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x3B:
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case 0x3B:
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/* INSQL */
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/* INSQL */
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gen_arith3_helper(helper_insql, ra, rb, rc, islit, lit);
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gen_arith3(helper_insql, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x3C:
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case 0x3C:
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/* SRA */
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/* SRA */
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@ -1243,11 +1231,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x52:
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case 0x52:
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/* MSKWH */
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/* MSKWH */
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gen_arith3_helper(helper_mskwh, ra, rb, rc, islit, lit);
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gen_arith3(helper_mskwh, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x57:
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case 0x57:
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/* INSWH */
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/* INSWH */
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gen_arith3_helper(helper_inswh, ra, rb, rc, islit, lit);
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gen_arith3(helper_inswh, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x5A:
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case 0x5A:
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/* EXTWH */
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/* EXTWH */
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@ -1255,11 +1243,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x62:
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case 0x62:
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/* MSKLH */
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/* MSKLH */
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gen_arith3_helper(helper_msklh, ra, rb, rc, islit, lit);
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gen_arith3(helper_msklh, ra, rb, rc, islit, lit);
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break;
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break;
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case 0x67:
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case 0x67:
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/* INSLH */
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/* INSLH */
|
||||||
gen_arith3_helper(helper_inslh, ra, rb, rc, islit, lit);
|
gen_arith3(helper_inslh, ra, rb, rc, islit, lit);
|
||||||
break;
|
break;
|
||||||
case 0x6A:
|
case 0x6A:
|
||||||
/* EXTLH */
|
/* EXTLH */
|
||||||
|
@ -1267,11 +1255,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
|
||||||
break;
|
break;
|
||||||
case 0x72:
|
case 0x72:
|
||||||
/* MSKQH */
|
/* MSKQH */
|
||||||
gen_arith3_helper(helper_mskqh, ra, rb, rc, islit, lit);
|
gen_arith3(helper_mskqh, ra, rb, rc, islit, lit);
|
||||||
break;
|
break;
|
||||||
case 0x77:
|
case 0x77:
|
||||||
/* INSQH */
|
/* INSQH */
|
||||||
gen_arith3_helper(helper_insqh, ra, rb, rc, islit, lit);
|
gen_arith3(helper_insqh, ra, rb, rc, islit, lit);
|
||||||
break;
|
break;
|
||||||
case 0x7A:
|
case 0x7A:
|
||||||
/* EXTQH */
|
/* EXTQH */
|
||||||
|
@ -1310,15 +1298,15 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
|
||||||
break;
|
break;
|
||||||
case 0x30:
|
case 0x30:
|
||||||
/* UMULH */
|
/* UMULH */
|
||||||
gen_arith3_helper(helper_umulh, ra, rb, rc, islit, lit);
|
gen_arith3(helper_umulh, ra, rb, rc, islit, lit);
|
||||||
break;
|
break;
|
||||||
case 0x40:
|
case 0x40:
|
||||||
/* MULL/V */
|
/* MULL/V */
|
||||||
gen_arith3_helper(helper_mullv, ra, rb, rc, islit, lit);
|
gen_arith3(helper_mullv, ra, rb, rc, islit, lit);
|
||||||
break;
|
break;
|
||||||
case 0x60:
|
case 0x60:
|
||||||
/* MULQ/V */
|
/* MULQ/V */
|
||||||
gen_arith3_helper(helper_mulqv, ra, rb, rc, islit, lit);
|
gen_arith3(helper_mulqv, ra, rb, rc, islit, lit);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
goto invalid_opc;
|
goto invalid_opc;
|
||||||
|
@ -2397,7 +2385,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
|
||||||
}
|
}
|
||||||
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
||||||
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
||||||
target_disas(logfile, pc_start, ctx.pc - pc_start, 1);
|
target_disas(logfile, pc_start, ctx.pc - pc_start, 1);
|
||||||
fprintf(logfile, "\n");
|
fprintf(logfile, "\n");
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Reference in a new issue