target/ppc: Style fixes for mmu_helper.c
Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
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@ -33,11 +33,11 @@
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#include "mmu-book3s-v3.h"
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#include "mmu-radix64.h"
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//#define DEBUG_MMU
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//#define DEBUG_BATS
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//#define DEBUG_SOFTWARE_TLB
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//#define DUMP_PAGE_TABLES
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//#define FLUSH_ALL_TLBS
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/* #define DEBUG_MMU */
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/* #define DEBUG_BATS */
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/* #define DEBUG_SOFTWARE_TLB */
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/* #define DUMP_PAGE_TABLES */
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/* #define FLUSH_ALL_TLBS */
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#ifdef DEBUG_MMU
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# define LOG_MMU_STATE(cpu) log_cpu_state_mask(CPU_LOG_MMU, (cpu), 0)
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@ -152,7 +152,8 @@ static int check_prot(int prot, int rw, int access_type)
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}
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static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0,
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target_ulong pte1, int h, int rw, int type)
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target_ulong pte1, int h,
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int rw, int type)
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{
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target_ulong ptem, mmask;
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int access, ret, pteh, ptev, pp;
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@ -332,7 +333,8 @@ static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx,
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pte_is_valid(tlb->pte0) ? "valid" : "inval",
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tlb->EPN, eaddr, tlb->pte1,
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rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
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switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
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switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1,
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0, rw, access_type)) {
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case -3:
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/* TLB inconsistency */
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return -1;
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@ -347,9 +349,11 @@ static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx,
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break;
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case 0:
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/* access granted */
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/* XXX: we should go on looping to check all TLBs consistency
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* but we can speed-up the whole thing as the
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* result would be undefined if TLBs are not consistent.
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/*
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* XXX: we should go on looping to check all TLBs
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* consistency but we can speed-up the whole thing as
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* the result would be undefined if TLBs are not
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* consistent.
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*/
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ret = 0;
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best = nr;
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@ -550,14 +554,18 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
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qemu_log_mask(CPU_LOG_MMU, "direct store...\n");
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/* Direct-store segment : absolutely *BUGGY* for now */
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/* Direct-store implies a 32-bit MMU.
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/*
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* Direct-store implies a 32-bit MMU.
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* Check the Segment Register's bus unit ID (BUID).
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*/
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sr = env->sr[eaddr >> 28];
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if ((sr & 0x1FF00000) >> 20 == 0x07f) {
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/* Memory-forced I/O controller interface access */
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/* If T=1 and BUID=x'07F', the 601 performs a memory access
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* to SR[28-31] LA[4-31], bypassing all protection mechanisms.
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/*
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* Memory-forced I/O controller interface access
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*
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* If T=1 and BUID=x'07F', the 601 performs a memory
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* access to SR[28-31] LA[4-31], bypassing all protection
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* mechanisms.
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*/
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ctx->raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
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ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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@ -578,9 +586,11 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
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/* lwarx, ldarx or srwcx. */
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return -4;
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case ACCESS_CACHE:
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/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
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/* Should make the instruction do no-op.
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* As it already do no-op, it's quite easy :-)
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/*
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* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi
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*
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* Should make the instruction do no-op. As it already do
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* no-op, it's quite easy :-)
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*/
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ctx->raddr = eaddr;
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return 0;
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@ -942,12 +952,14 @@ static uint32_t mmubooke206_esr(int mmu_idx, bool rw)
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return esr;
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}
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/* Get EPID register given the mmu_idx. If this is regular load,
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* construct the EPID access bits from current processor state */
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/* Get the effective AS and PR bits and the PID. The PID is returned only if
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* EPID load is requested, otherwise the caller must detect the correct EPID.
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* Return true if valid EPID is returned. */
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/*
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* Get EPID register given the mmu_idx. If this is regular load,
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* construct the EPID access bits from current processor state
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*
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* Get the effective AS and PR bits and the PID. The PID is returned
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* only if EPID load is requested, otherwise the caller must detect
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* the correct EPID. Return true if valid EPID is returned.
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*/
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static bool mmubooke206_get_as(CPUPPCState *env,
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int mmu_idx, uint32_t *epid_out,
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bool *as_out, bool *pr_out)
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@ -1369,8 +1381,9 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx,
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case POWERPC_MMU_SOFT_4xx_Z:
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if (unlikely(msr_pe != 0)) {
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/* 403 family add some particular protections,
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* using PBL/PBU registers for accesses with no translation.
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/*
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* 403 family add some particular protections, using
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* PBL/PBU registers for accesses with no translation.
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*/
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in_plb =
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/* Check PLB validity */
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@ -1453,7 +1466,8 @@ static int get_physical_address_wtlb(
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if (real_mode) {
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ret = check_physical(env, ctx, eaddr, rw);
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} else {
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cpu_abort(CPU(cpu), "PowerPC in real mode do not do any translation\n");
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cpu_abort(CPU(cpu),
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"PowerPC in real mode do not do any translation\n");
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}
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return -1;
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default:
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@ -1498,9 +1512,10 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) {
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/* Some MMUs have separate TLBs for code and data. If we only try an
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* ACCESS_INT, we may not be able to read instructions mapped by code
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* TLBs, so we also try a ACCESS_CODE.
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/*
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* Some MMUs have separate TLBs for code and data. If we only
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* try an ACCESS_INT, we may not be able to read instructions
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* mapped by code TLBs, so we also try a ACCESS_CODE.
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*/
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if (unlikely(get_physical_address(env, &ctx, addr, 0,
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ACCESS_CODE) != 0)) {
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@ -1834,8 +1849,9 @@ void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong value)
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#if !defined(FLUSH_ALL_TLBS)
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do_invalidate_BAT(env, env->IBAT[0][nr], mask);
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#endif
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/* When storing valid upper BAT, mask BEPI and BRPN
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* and invalidate all TLBs covered by this BAT
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/*
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* When storing valid upper BAT, mask BEPI and BRPN and
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* invalidate all TLBs covered by this BAT
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*/
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mask = (value << 15) & 0x0FFE0000UL;
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env->IBAT[0][nr] = (value & 0x00001FFFUL) |
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@ -1865,8 +1881,9 @@ void helper_store_dbatu(CPUPPCState *env, uint32_t nr, target_ulong value)
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dump_store_bat(env, 'D', 0, nr, value);
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if (env->DBAT[0][nr] != value) {
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/* When storing valid upper BAT, mask BEPI and BRPN
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* and invalidate all TLBs covered by this BAT
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/*
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* When storing valid upper BAT, mask BEPI and BRPN and
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* invalidate all TLBs covered by this BAT
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*/
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mask = (value << 15) & 0x0FFE0000UL;
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#if !defined(FLUSH_ALL_TLBS)
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@ -1913,8 +1930,9 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t nr, target_ulong value)
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do_inval = 1;
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#endif
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}
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/* When storing valid upper BAT, mask BEPI and BRPN
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* and invalidate all TLBs covered by this BAT
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/*
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* When storing valid upper BAT, mask BEPI and BRPN and
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* invalidate all TLBs covered by this BAT
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*/
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env->IBAT[0][nr] = (value & 0x00001FFFUL) |
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(value & ~0x0001FFFFUL & ~mask);
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@ -2027,7 +2045,8 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
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#if defined(TARGET_PPC64)
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if (env->mmu_model & POWERPC_MMU_64) {
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/* tlbie invalidate TLBs for all segments */
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/* XXX: given the fact that there are too many segments to invalidate,
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/*
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* XXX: given the fact that there are too many segments to invalidate,
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* and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,
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* we just invalidate all TLBs
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*/
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@ -2044,10 +2063,11 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
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break;
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case POWERPC_MMU_32B:
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case POWERPC_MMU_601:
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/* Actual CPUs invalidate entire congruence classes based on the
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* geometry of their TLBs and some OSes take that into account,
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* we just mark the TLB to be flushed later (context synchronizing
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* event or sync instruction on 32-bit).
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/*
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* Actual CPUs invalidate entire congruence classes based on
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* the geometry of their TLBs and some OSes take that into
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* account, we just mark the TLB to be flushed later (context
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* synchronizing event or sync instruction on 32-bit).
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*/
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env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
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break;
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@ -2152,8 +2172,10 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
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#endif
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if (env->sr[srnum] != value) {
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env->sr[srnum] = value;
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/* Invalidating 256MB of virtual memory in 4kB pages is way longer than
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flusing the whole TLB. */
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/*
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* Invalidating 256MB of virtual memory in 4kB pages is way
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* longer than flusing the whole TLB.
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*/
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#if !defined(FLUSH_ALL_TLBS) && 0
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{
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target_ulong page, end;
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@ -2264,10 +2286,12 @@ target_ulong helper_rac(CPUPPCState *env, target_ulong addr)
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int nb_BATs;
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target_ulong ret = 0;
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/* We don't have to generate many instances of this instruction,
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/*
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* We don't have to generate many instances of this instruction,
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* as rac is supervisor only.
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*
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* XXX: FIX THIS: Pretend we have no BAT
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*/
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/* XXX: FIX THIS: Pretend we have no BAT */
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nb_BATs = env->nb_BATs;
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env->nb_BATs = 0;
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if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0) {
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@ -2422,7 +2446,8 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
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}
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tlb->size = booke_tlb_to_page_size((val >> PPC4XX_TLBHI_SIZE_SHIFT)
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& PPC4XX_TLBHI_SIZE_MASK);
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/* We cannot handle TLB size < TARGET_PAGE_SIZE.
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/*
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* We cannot handle TLB size < TARGET_PAGE_SIZE.
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* If this ever occurs, we should implement TARGET_PAGE_BITS_VARY
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*/
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if ((val & PPC4XX_TLBHI_V) && tlb->size < TARGET_PAGE_SIZE) {
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@ -2742,7 +2767,8 @@ void helper_booke206_tlbwe(CPUPPCState *env)
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}
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if (tlb->mas1 & MAS1_VALID) {
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/* Invalidate the page in QEMU TLB if it was a valid entry.
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/*
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* Invalidate the page in QEMU TLB if it was a valid entry.
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*
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* In "PowerPC e500 Core Family Reference Manual, Rev. 1",
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* Section "12.4.2 TLB Write Entry (tlbwe) Instruction":
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* "Note that when an L2 TLB entry is written, it may be displacing an
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* already valid entry in the same L2 TLB location (a victim). If a
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* valid L1 TLB entry corresponds to the L2 MMU victim entry, that L1
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* TLB entry is automatically invalidated." */
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* TLB entry is automatically invalidated."
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*/
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flush_page(env, tlb);
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}
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mask |= MAS2_ACM | MAS2_VLE | MAS2_W | MAS2_I | MAS2_M | MAS2_G | MAS2_E;
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if (!msr_cm) {
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/* Executing a tlbwe instruction in 32-bit mode will set
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* bits 0:31 of the TLB EPN field to zero.
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/*
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* Executing a tlbwe instruction in 32-bit mode will set bits
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* 0:31 of the TLB EPN field to zero.
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*/
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mask &= 0xffffffff;
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}
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/*****************************************************************************/
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/* try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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/* XXX: fix it to restore all registers */
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/*
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* try to fill the TLB and return an exception if error. If retaddr is
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* NULL, it means that the function was called in C code (i.e. not
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* from generated code or from helper.c)
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*
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* XXX: fix it to restore all registers
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*/
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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