target/m68k: Convert to CPUClass::tlb_fill
Cc: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -269,7 +269,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
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cc->set_pc = m68k_cpu_set_pc;
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cc->gdb_read_register = m68k_cpu_gdb_read_register;
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cc->gdb_write_register = m68k_cpu_gdb_write_register;
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cc->handle_mmu_fault = m68k_cpu_handle_mmu_fault;
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cc->tlb_fill = m68k_cpu_tlb_fill;
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#if defined(CONFIG_SOFTMMU)
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cc->do_unassigned_access = m68k_cpu_unassigned_access;
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cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
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@ -542,8 +542,9 @@ static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
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return (env->sr & SR_S) == 0 ? 1 : 0;
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}
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int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
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int mmu_idx);
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bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr,
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bool is_write, bool is_exec, int is_asi,
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unsigned size);
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@ -353,20 +353,7 @@ void m68k_switch_sp(CPUM68KState *env)
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env->current_sp = new_sp;
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}
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#if defined(CONFIG_USER_ONLY)
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int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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int mmu_idx)
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{
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M68kCPU *cpu = M68K_CPU(cs);
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cs->exception_index = EXCP_ACCESS;
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cpu->env.mmu.ar = address;
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return 1;
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}
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#else
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#if !defined(CONFIG_USER_ONLY)
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/* MMU: 68040 only */
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static void print_address_zone(uint32_t logical, uint32_t physical,
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@ -795,11 +782,36 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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return phys_addr;
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}
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int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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int mmu_idx)
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/*
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* Notify CPU of a pending interrupt. Prioritization and vectoring should
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* be handled by the interrupt controller. Real hardware only requests
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* the vector when the interrupt is acknowledged by the CPU. For
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* simplicity we calculate it when the interrupt is signalled.
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*/
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void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector)
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{
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CPUState *cs = CPU(cpu);
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CPUM68KState *env = &cpu->env;
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env->pending_level = level;
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env->pending_vector = vector;
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if (level) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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#endif
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bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType qemu_access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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M68kCPU *cpu = M68K_CPU(cs);
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CPUM68KState *env = &cpu->env;
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#ifndef CONFIG_USER_ONLY
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hwaddr physical;
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int prot;
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int access_type;
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@ -812,32 +824,35 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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address & TARGET_PAGE_MASK,
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PAGE_READ | PAGE_WRITE | PAGE_EXEC,
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mmu_idx, TARGET_PAGE_SIZE);
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return 0;
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return true;
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}
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if (rw == 2) {
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if (qemu_access_type == MMU_INST_FETCH) {
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access_type = ACCESS_CODE;
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rw = 0;
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} else {
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access_type = ACCESS_DATA;
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if (rw) {
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if (qemu_access_type == MMU_DATA_STORE) {
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access_type |= ACCESS_STORE;
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}
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}
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if (mmu_idx != MMU_USER_IDX) {
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access_type |= ACCESS_SUPER;
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}
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ret = get_physical_address(&cpu->env, &physical, &prot,
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address, access_type, &page_size);
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if (ret == 0) {
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if (likely(ret == 0)) {
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address &= TARGET_PAGE_MASK;
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physical += address & (page_size - 1);
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tlb_set_page(cs, address, physical,
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prot, mmu_idx, TARGET_PAGE_SIZE);
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return 0;
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return true;
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}
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if (probe) {
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return false;
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}
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/* page fault */
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env->mmu.ssw = M68K_ATC_040;
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switch (size) {
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@ -862,29 +877,19 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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if (!(access_type & ACCESS_STORE)) {
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env->mmu.ssw |= M68K_RW_040;
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}
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env->mmu.ar = address;
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#endif
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cs->exception_index = EXCP_ACCESS;
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return 1;
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env->mmu.ar = address;
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cpu_loop_exit_restore(cs, retaddr);
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}
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/* Notify CPU of a pending interrupt. Prioritization and vectoring should
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be handled by the interrupt controller. Real hardware only requests
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the vector when the interrupt is acknowledged by the CPU. For
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simplicitly we calculate it when the interrupt is signalled. */
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void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector)
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#ifndef CONFIG_USER_ONLY
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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CPUState *cs = CPU(cpu);
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CPUM68KState *env = &cpu->env;
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env->pending_level = level;
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env->pending_vector = vector;
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if (level) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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m68k_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
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}
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#endif
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uint32_t HELPER(bitrev)(uint32_t x)
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@ -36,21 +36,6 @@ static inline void do_interrupt_m68k_hardirq(CPUM68KState *env)
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#else
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/* Try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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int ret;
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ret = m68k_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
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if (unlikely(ret)) {
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/* now we have a real cpu fault */
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cpu_loop_exit_restore(cs, retaddr);
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}
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}
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static void cf_rte(CPUM68KState *env)
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{
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uint32_t sp;
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