target/mips: Amend CP0 WatchHi register implementation
WatchHi is extended by the field MemoryMapID with the GINVT instruction. The field is accessible by MTHC0/MFHC0 in 32-bit architectures and DMTC0/ DMFC0 in 64-bit architectures. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1579883929-1517-4-git-send-email-aleksandar.markovic@rt-rk.com>
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@ -961,7 +961,7 @@ struct CPUMIPSState {
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/*
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* CP0 Register 19
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*/
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int32_t CP0_WatchHi[8];
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uint64_t CP0_WatchHi[8];
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#define CP0WH_ASID 16
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/*
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* CP0 Register 20
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@ -78,6 +78,7 @@ DEF_HELPER_1(mfc0_maar, tl, env)
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DEF_HELPER_1(mfhc0_maar, tl, env)
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DEF_HELPER_2(mfc0_watchlo, tl, env, i32)
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DEF_HELPER_2(mfc0_watchhi, tl, env, i32)
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DEF_HELPER_2(mfhc0_watchhi, tl, env, i32)
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DEF_HELPER_1(mfc0_debug, tl, env)
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DEF_HELPER_1(mftc0_debug, tl, env)
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#ifdef TARGET_MIPS64
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@ -89,6 +90,7 @@ DEF_HELPER_1(dmfc0_tcschefback, tl, env)
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DEF_HELPER_1(dmfc0_lladdr, tl, env)
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DEF_HELPER_1(dmfc0_maar, tl, env)
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DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
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DEF_HELPER_2(dmfc0_watchhi, tl, env, i32)
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DEF_HELPER_1(dmfc0_saar, tl, env)
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#endif /* TARGET_MIPS64 */
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@ -159,6 +161,7 @@ DEF_HELPER_2(mthc0_maar, void, env, tl)
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DEF_HELPER_2(mtc0_maari, void, env, tl)
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DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
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DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
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DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32)
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DEF_HELPER_2(mtc0_xcontext, void, env, tl)
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DEF_HELPER_2(mtc0_framemask, void, env, tl)
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DEF_HELPER_2(mtc0_debug, void, env, tl)
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@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = {
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const VMStateDescription vmstate_mips_cpu = {
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.name = "cpu",
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.version_id = 18,
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.minimum_version_id = 18,
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.version_id = 19,
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.minimum_version_id = 19,
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.post_load = cpu_post_load,
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.fields = (VMStateField[]) {
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/* Active TC */
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@ -296,7 +296,7 @@ const VMStateDescription vmstate_mips_cpu = {
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VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
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VMSTATE_UINTTL(env.lladdr, MIPSCPU),
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VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
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VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
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VMSTATE_UINT64_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
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VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
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VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
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VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
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@ -945,7 +945,12 @@ target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
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target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
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{
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return env->CP0_WatchHi[sel];
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return (int32_t) env->CP0_WatchHi[sel];
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}
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target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel)
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{
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return env->CP0_WatchHi[sel] >> 32;
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}
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target_ulong helper_mfc0_debug(CPUMIPSState *env)
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@ -1016,6 +1021,11 @@ target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
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return env->CP0_WatchLo[sel];
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}
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target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel)
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{
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return env->CP0_WatchHi[sel];
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}
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target_ulong helper_dmfc0_saar(CPUMIPSState *env)
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{
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if ((env->CP0_SAARI & 0x3f) < 2) {
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@ -1869,11 +1879,20 @@ void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
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void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
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{
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int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
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uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
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if ((env->CP0_Config5 >> CP0C5_MI) & 1) {
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mask |= 0xFFFFFFFF00000000ULL; /* MMID */
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}
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env->CP0_WatchHi[sel] = arg1 & mask;
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env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
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}
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void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
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{
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env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) |
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(env->CP0_WatchHi[sel] & 0x00000000ffffffffULL);
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}
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void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
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{
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target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
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@ -2547,6 +2547,7 @@ typedef struct DisasContext {
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bool nan2008;
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bool abs2008;
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bool saar;
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bool mi;
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} DisasContext;
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#define DISAS_STOP DISAS_TARGET_0
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@ -6783,6 +6784,25 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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goto cp0_unimplemented;
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}
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break;
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case CP0_REGISTER_19:
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switch (sel) {
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case CP0_REG19__WATCHHI0:
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case CP0_REG19__WATCHHI1:
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case CP0_REG19__WATCHHI2:
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case CP0_REG19__WATCHHI3:
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case CP0_REG19__WATCHHI4:
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case CP0_REG19__WATCHHI5:
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case CP0_REG19__WATCHHI6:
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case CP0_REG19__WATCHHI7:
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/* upper 32 bits are only available when Config5MI != 0 */
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CP0_CHECK(ctx->mi);
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gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_WatchHi[sel]), 0);
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register_name = "WatchHi";
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break;
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default:
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goto cp0_unimplemented;
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}
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break;
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case CP0_REGISTER_28:
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switch (sel) {
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case 0:
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@ -6869,6 +6889,25 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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goto cp0_unimplemented;
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}
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break;
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case CP0_REGISTER_19:
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switch (sel) {
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case CP0_REG19__WATCHHI0:
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case CP0_REG19__WATCHHI1:
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case CP0_REG19__WATCHHI2:
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case CP0_REG19__WATCHHI3:
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case CP0_REG19__WATCHHI4:
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case CP0_REG19__WATCHHI5:
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case CP0_REG19__WATCHHI6:
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case CP0_REG19__WATCHHI7:
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/* upper 32 bits are only available when Config5MI != 0 */
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CP0_CHECK(ctx->mi);
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gen_helper_0e1i(mthc0_watchhi, arg, sel);
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register_name = "WatchHi";
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break;
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default:
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goto cp0_unimplemented;
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}
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break;
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case CP0_REGISTER_28:
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switch (sel) {
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case 0:
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@ -8922,7 +8961,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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case CP0_REG19__WATCHHI6:
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case CP0_REG19__WATCHHI7:
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CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
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gen_helper_1e0i(mfc0_watchhi, arg, sel);
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gen_helper_1e0i(dmfc0_watchhi, arg, sel);
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register_name = "WatchHi";
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break;
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default:
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@ -30727,6 +30766,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
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ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
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ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
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ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1;
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restore_cpu_state(env, ctx);
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#ifdef CONFIG_USER_ONLY
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ctx->mem_idx = MIPS_HFLAG_UM;
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