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target/xtensa: move FSR/FCR register accessors

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Move FSR/FCR register accessors from core opcodes to FPU2000 opcodes as
they are FPU2000-specific.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2015-07-13 04:30:41 +03:00
parent 5680f20756
commit ff35a7d1a1
1 changed files with 32 additions and 32 deletions
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64
target/xtensa/translate.c
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@ -2813,18 +2813,6 @@ static void translate_wur(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in);
}
static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in);
}
static void translate_wur_fsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80);
}
static void translate_xor(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
@ -4665,16 +4653,6 @@ static const XtensaOpcodeOps core_ops[] = {
.name = "rur.expstate",
.translate = translate_rur,
.par = (const uint32_t[]){EXPSTATE},
}, {
.name = "rur.fcr",
.translate = translate_rur,
.par = (const uint32_t[]){FCR},
.coprocessor = 0x1,
}, {
.name = "rur.fsr",
.translate = translate_rur,
.par = (const uint32_t[]){FSR},
.coprocessor = 0x1,
}, {
.name = "rur.threadptr",
.translate = translate_rur,
@ -5581,16 +5559,6 @@ static const XtensaOpcodeOps core_ops[] = {
.name = "wur.expstate",
.translate = translate_wur,
.par = (const uint32_t[]){EXPSTATE},
}, {
.name = "wur.fcr",
.translate = translate_wur_fpu2k_fcr,
.par = (const uint32_t[]){FCR},
.coprocessor = 0x1,
}, {
.name = "wur.fsr",
.translate = translate_wur_fsr,
.par = (const uint32_t[]){FSR},
.coprocessor = 0x1,
}, {
.name = "wur.threadptr",
.translate = translate_wur,
@ -6510,6 +6478,18 @@ static void translate_wfr_s(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_mov_i32(arg[0].out, arg[1].in);
}
static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in);
}
static void translate_wur_fpu2k_fsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80);
}
static const XtensaOpcodeOps fpu2000_ops[] = {
{
.name = "abs.s",
@ -6632,6 +6612,16 @@ static const XtensaOpcodeOps fpu2000_ops[] = {
.translate = translate_ftoi_s,
.par = (const uint32_t[]){float_round_nearest_even, false},
.coprocessor = 0x1,
}, {
.name = "rur.fcr",
.translate = translate_rur,
.par = (const uint32_t[]){FCR},
.coprocessor = 0x1,
}, {
.name = "rur.fsr",
.translate = translate_rur,
.par = (const uint32_t[]){FSR},
.coprocessor = 0x1,
}, {
.name = "ssi",
.translate = translate_ldsti,
@ -6699,6 +6689,16 @@ static const XtensaOpcodeOps fpu2000_ops[] = {
.name = "wfr",
.translate = translate_wfr_s,
.coprocessor = 0x1,
}, {
.name = "wur.fcr",
.translate = translate_wur_fpu2k_fcr,
.par = (const uint32_t[]){FCR},
.coprocessor = 0x1,
}, {
.name = "wur.fsr",
.translate = translate_wur_fpu2k_fsr,
.par = (const uint32_t[]){FSR},
.coprocessor = 0x1,
},
};