ast2400: replace ast2400 with aspeed_soc
This is a name replacement to prepare ground for other SoCs. Let's also remove the AST2400_SMC_BASE definition from the address space mappings, as it is not used. This controller was removed from the Aspeed SoC AST2500, so this provides us a better common base for the address space mapping on both SoCs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-3-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
00442402ea
commit
ff90606f9a
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@ -1,5 +1,5 @@
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/*
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/*
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* AST2400 SoC
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* ASPEED SoC family
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*
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*
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* Andrew Jeffery <andrew@aj.id.au>
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* Andrew Jeffery <andrew@aj.id.au>
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* Jeremy Kerr <jk@ozlabs.org>
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* Jeremy Kerr <jk@ozlabs.org>
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@ -20,20 +20,19 @@
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#include "qemu/log.h"
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#include "qemu/log.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "hw/i2c/aspeed_i2c.h"
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#define AST2400_UART_5_BASE 0x00184000
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#define ASPEED_SOC_UART_5_BASE 0x00184000
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#define AST2400_IOMEM_SIZE 0x00200000
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#define ASPEED_SOC_IOMEM_SIZE 0x00200000
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#define AST2400_IOMEM_BASE 0x1E600000
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#define ASPEED_SOC_IOMEM_BASE 0x1E600000
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#define AST2400_SMC_BASE AST2400_IOMEM_BASE /* Legacy SMC */
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#define ASPEED_SOC_FMC_BASE 0x1E620000
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#define AST2400_FMC_BASE 0X1E620000
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#define ASPEED_SOC_SPI_BASE 0x1E630000
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#define AST2400_SPI_BASE 0X1E630000
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#define ASPEED_SOC_VIC_BASE 0x1E6C0000
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#define AST2400_VIC_BASE 0x1E6C0000
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#define ASPEED_SOC_SDMC_BASE 0x1E6E0000
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#define AST2400_SDMC_BASE 0x1E6E0000
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#define ASPEED_SOC_SCU_BASE 0x1E6E2000
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#define AST2400_SCU_BASE 0x1E6E2000
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#define ASPEED_SOC_TIMER_BASE 0x1E782000
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#define AST2400_TIMER_BASE 0x1E782000
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#define ASPEED_SOC_I2C_BASE 0x1E78A000
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#define AST2400_I2C_BASE 0x1E78A000
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#define AST2400_FMC_FLASH_BASE 0x20000000
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#define ASPEED_SOC_FMC_FLASH_BASE 0x20000000
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#define AST2400_SPI_FLASH_BASE 0x30000000
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#define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
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static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
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static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
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static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
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static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
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@ -43,29 +42,29 @@ static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
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* handled by a device mapping.
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* handled by a device mapping.
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*/
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*/
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static uint64_t ast2400_io_read(void *p, hwaddr offset, unsigned size)
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static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size)
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{
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{
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qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
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qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
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__func__, offset, size);
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__func__, offset, size);
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return 0;
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return 0;
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}
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}
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static void ast2400_io_write(void *opaque, hwaddr offset, uint64_t value,
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static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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unsigned size)
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{
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{
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qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
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qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
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__func__, offset, value, size);
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__func__, offset, value, size);
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}
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}
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static const MemoryRegionOps ast2400_io_ops = {
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static const MemoryRegionOps aspeed_soc_io_ops = {
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.read = ast2400_io_read,
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.read = aspeed_soc_io_read,
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.write = ast2400_io_write,
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.write = aspeed_soc_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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};
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static void ast2400_init(Object *obj)
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static void aspeed_soc_init(Object *obj)
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{
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{
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AST2400State *s = AST2400(obj);
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AspeedSoCState *s = ASPEED_SOC(obj);
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s->cpu = cpu_arm_init("arm926");
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s->cpu = cpu_arm_init("arm926");
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@ -106,17 +105,17 @@ static void ast2400_init(Object *obj)
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AST2400_A0_SILICON_REV);
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AST2400_A0_SILICON_REV);
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}
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}
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static void ast2400_realize(DeviceState *dev, Error **errp)
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static void aspeed_soc_realize(DeviceState *dev, Error **errp)
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{
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{
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int i;
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int i;
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AST2400State *s = AST2400(dev);
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AspeedSoCState *s = ASPEED_SOC(dev);
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Error *err = NULL, *local_err = NULL;
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Error *err = NULL, *local_err = NULL;
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/* IO space */
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/* IO space */
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memory_region_init_io(&s->iomem, NULL, &ast2400_io_ops, NULL,
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memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL,
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"ast2400.io", AST2400_IOMEM_SIZE);
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"aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE);
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memory_region_add_subregion_overlap(get_system_memory(), AST2400_IOMEM_BASE,
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memory_region_add_subregion_overlap(get_system_memory(),
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&s->iomem, -1);
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ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);
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/* VIC */
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/* VIC */
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object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
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object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
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@ -124,7 +123,7 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
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error_propagate(errp, err);
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error_propagate(errp, err);
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return;
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return;
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}
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, AST2400_VIC_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
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qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
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qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
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@ -136,7 +135,7 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
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error_propagate(errp, err);
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error_propagate(errp, err);
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return;
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return;
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}
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, AST2400_TIMER_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
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for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
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for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
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qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
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qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
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@ -148,12 +147,12 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
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error_propagate(errp, err);
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error_propagate(errp, err);
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return;
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return;
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}
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, AST2400_SCU_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
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/* UART - attach an 8250 to the IO space as our UART5 */
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/* UART - attach an 8250 to the IO space as our UART5 */
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if (serial_hds[0]) {
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if (serial_hds[0]) {
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qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
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qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
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serial_mm_init(&s->iomem, AST2400_UART_5_BASE, 2,
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serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,
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uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
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uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
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}
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}
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@ -163,7 +162,7 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
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error_propagate(errp, err);
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error_propagate(errp, err);
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return;
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return;
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}
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, AST2400_I2C_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
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qdev_get_gpio_in(DEVICE(&s->vic), 12));
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qdev_get_gpio_in(DEVICE(&s->vic), 12));
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@ -175,8 +174,8 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
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error_propagate(errp, err);
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error_propagate(errp, err);
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return;
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return;
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}
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 0, AST2400_FMC_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 0, ASPEED_SOC_FMC_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 1, AST2400_FMC_FLASH_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 1, ASPEED_SOC_FMC_FLASH_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->smc), 0,
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->smc), 0,
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qdev_get_gpio_in(DEVICE(&s->vic), 19));
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qdev_get_gpio_in(DEVICE(&s->vic), 19));
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@ -188,8 +187,8 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
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error_propagate(errp, err);
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error_propagate(errp, err);
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return;
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return;
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}
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, AST2400_SPI_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, ASPEED_SOC_SPI_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, AST2400_SPI_FLASH_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, ASPEED_SOC_SPI_FLASH_BASE);
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/* SDMC - SDRAM Memory Controller */
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/* SDMC - SDRAM Memory Controller */
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object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
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object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
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@ -197,14 +196,14 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
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error_propagate(errp, err);
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error_propagate(errp, err);
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return;
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return;
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}
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, AST2400_SDMC_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
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}
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}
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static void ast2400_class_init(ObjectClass *oc, void *data)
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static void aspeed_soc_class_init(ObjectClass *oc, void *data)
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{
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = ast2400_realize;
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dc->realize = aspeed_soc_realize;
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/*
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/*
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* Reason: creates an ARM CPU, thus use after free(), see
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* Reason: creates an ARM CPU, thus use after free(), see
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dc->cannot_destroy_with_object_finalize_yet = true;
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dc->cannot_destroy_with_object_finalize_yet = true;
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}
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}
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static const TypeInfo ast2400_type_info = {
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static const TypeInfo aspeed_soc_type_info = {
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.name = TYPE_AST2400,
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.name = TYPE_ASPEED_SOC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AST2400State),
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.instance_size = sizeof(AspeedSoCState),
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.instance_init = ast2400_init,
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.instance_init = aspeed_soc_init,
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.class_init = ast2400_class_init,
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.class_init = aspeed_soc_class_init,
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};
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};
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static void ast2400_register_types(void)
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static void aspeed_soc_register_types(void)
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{
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{
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type_register_static(&ast2400_type_info);
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type_register_static(&aspeed_soc_type_info);
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}
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}
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type_init(ast2400_register_types)
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type_init(aspeed_soc_register_types)
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};
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};
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typedef struct PalmettoBMCState {
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typedef struct PalmettoBMCState {
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AST2400State soc;
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AspeedSoCState soc;
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MemoryRegion ram;
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MemoryRegion ram;
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} PalmettoBMCState;
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} PalmettoBMCState;
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PalmettoBMCState *bmc;
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PalmettoBMCState *bmc;
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bmc = g_new0(PalmettoBMCState, 1);
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bmc = g_new0(PalmettoBMCState, 1);
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object_initialize(&bmc->soc, (sizeof(bmc->soc)), TYPE_AST2400);
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object_initialize(&bmc->soc, (sizeof(bmc->soc)), TYPE_ASPEED_SOC);
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object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc),
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object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc),
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&error_abort);
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&error_abort);
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@ -1,5 +1,5 @@
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/*
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/*
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* ASPEED AST2400 SoC
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* ASPEED SoC family
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*
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*
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* Andrew Jeffery <andrew@aj.id.au>
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* Andrew Jeffery <andrew@aj.id.au>
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*
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*
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* the COPYING file in the top-level directory.
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* the COPYING file in the top-level directory.
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*/
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*/
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#ifndef AST2400_H
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#ifndef ASPEED_SOC_H
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#define AST2400_H
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#define ASPEED_SOC_H
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#include "hw/arm/arm.h"
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#include "hw/arm/arm.h"
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#include "hw/intc/aspeed_vic.h"
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#include "hw/intc/aspeed_vic.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "hw/ssi/aspeed_smc.h"
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#include "hw/ssi/aspeed_smc.h"
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typedef struct AST2400State {
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typedef struct AspeedSoCState {
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/*< private >*/
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/*< private >*/
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DeviceState parent;
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DeviceState parent;
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AspeedSMCState smc;
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AspeedSMCState smc;
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AspeedSMCState spi;
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AspeedSMCState spi;
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AspeedSDMCState sdmc;
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AspeedSDMCState sdmc;
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} AST2400State;
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} AspeedSoCState;
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#define TYPE_AST2400 "ast2400"
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#define TYPE_ASPEED_SOC "aspeed-soc"
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#define AST2400(obj) OBJECT_CHECK(AST2400State, (obj), TYPE_AST2400)
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#define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
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#define AST2400_SDRAM_BASE 0x40000000
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#define AST2400_SDRAM_BASE 0x40000000
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#endif /* AST2400_H */
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#endif /* ASPEED_SOC_H */
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