Commit graph

2 commits

Author SHA1 Message Date
Max Filippov fa92bd4af7 target/xtensa: fix access to the INTERRUPT SR
INTERRUPT special register may be changed both by the core (by writing
to INTSET and INTCLEAR registers) and by external events (by triggering
and clearing HW IRQs). In MTTCG this state must be protected from
concurrent access, otherwise interrupts may be lost or spurious
interrupts may be detected.

Use atomic operations to change INTSET SR.
Fix wsr.intset so that it soesn't clear any bits.
Fix wsr.intclear so that it doesn't clear bit that corresponds to NMI.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-24 10:44:26 -08:00
Max Filippov 8d918d656a target/xtensa: extract interrupt and exception helpers
Move helper functions related to interrupt and exception handling from
op_helper.c and helper.c to exc_helper.c. No functional changes.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-13 23:36:29 -08:00