ths
a6763a5881
Fix MIPS64 address computation specialcase, by Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2793 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-09 09:33:33 +00:00
ths
5a5012ecbd
MIPS 64-bit FPU support, plus some collateral bugfixes in the
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conditional branch handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2779 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-07 13:55:33 +00:00
ths
d6929309b6
Next attempt to get the lui sign extension right.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2727 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-25 16:41:11 +00:00
ths
7bc45061ee
Fix lui sign extension.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2726 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-25 13:58:52 +00:00
ths
fcb4a419f5
Choose number of TLBs at runtime, by Herve Poussineau.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2693 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-17 15:26:47 +00:00
ths
9898128f55
Simplify branch likely handling.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2676 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-16 01:35:29 +00:00
ths
171b31e7c7
Don't use T2 for INS, it conflicts with branch delay slot handling.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2674 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-15 21:26:37 +00:00
ths
a85427b147
Small code generation optimization.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2672 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-15 19:52:12 +00:00
ths
16c00cb2c2
Restart interrupts after an exception.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2664 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-14 12:56:46 +00:00
ths
2f6445458e
Make SYNCI_Step and CCRes CPU-specific.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2651 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-11 20:34:23 +00:00
ths
b48cfdffd9
Throw RI for invalid MFMC0-class instructions. Introduce optional
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MIPS_STRICT_STANDARD define to adhere more to the spec than it makes
sense in normal operation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2650 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-11 02:24:14 +00:00
ths
2423f6601a
Code formatting fix.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2649 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-11 02:15:08 +00:00
ths
534ce69ff0
More Context/Xcontext fixes. Ifdef some 64bit-only ops, they may
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end up empty for 32bit mips, which dyngen trips over.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2648 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-11 02:13:00 +00:00
ths
c090a8f440
Fix CP0_IntCtl handling.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2645 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-09 14:17:31 +00:00
ths
4e7a4a4e84
Mark watchpoint features as unimplemented.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2643 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-09 14:15:41 +00:00
ths
62c5609aa5
Catch unaligned sc/scd.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2642 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-09 14:14:21 +00:00
ths
97428a4d84
Fix exception handling cornercase for rdhwr.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2641 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-09 14:13:40 +00:00
ths
dac9321024
Remove bogus mtc0 handling.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2640 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-09 12:31:31 +00:00
ths
e0c84da78c
Implement prefx.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2630 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-07 01:11:39 +00:00
ths
cbeb0857da
Set proper BadVAddress value for unaligned instruction fetch.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2629 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-07 01:11:15 +00:00
ths
e04bcc691b
Actually skip over delay slot for a non-taken branch likely.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2628 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-07 01:10:22 +00:00
ths
f41c52f170
Save state for all CP0 instructions, they may throw a CPU exception.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2622 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-06 18:46:01 +00:00
ths
c53f4a62e3
fix branch delay slot cornercases.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2615 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-05 23:21:37 +00:00
ths
5a63bcb2d2
Fix rotr immediate ops, mask shift/rotate arguments to their allowed
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size.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2614 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-05 23:20:05 +00:00
ths
1579a72ec5
Fix RDHWR handling. Code formatting. Don't use *_direct versions to raise
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exceptions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2611 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-05 23:16:25 +00:00
ths
876d4b0783
Fix code formatting.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2595 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-04 21:07:17 +00:00
ths
38121543c7
MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registers
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are implemented.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2589 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-02 17:28:07 +00:00
ths
60aa19abef
Actually enable 64bit configuration.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2565 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-01 12:36:18 +00:00
ths
24c7b0e330
Sanitize mips exception handling.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2546 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-30 16:44:54 +00:00
ths
e397ee3382
Fix enough FPU/R2 support to get 24Kf going.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2528 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-23 00:43:28 +00:00
ths
3953d78687
Move mips CPU specific initialization to translate_init.c.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2522 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-21 11:04:42 +00:00
ths
3ad4bb2d3d
Barf on branches/jumps in branch delay slots. Spotted by Stefan Weil.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2513 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-19 22:15:30 +00:00
ths
820e00f252
Define gen_intermediate_code_internal as "static inline".
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2512 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-19 21:46:06 +00:00
ths
33d68b5f00
MIPS -cpu selection support, by Herve Poussineau.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2491 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-18 00:30:29 +00:00
ths
6f5b89a07c
MIPS Userland TLS register emulation, by Daniel Jacobowitz.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2465 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-02 20:48:00 +00:00
ths
36d2395873
MIPS FPU dynamic activation, part 1, by Herve Poussineau.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2463 c046a42c-6fe2-441c-8c8c-71466251a162
2007-02-28 22:37:42 +00:00
ths
00a709c7b9
Fix mips FPU emulation, 32 bit data types are allowed to use odd registers.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2454 c046a42c-6fe2-441c-8c8c-71466251a162
2007-02-27 19:27:51 +00:00
ths
3594c77487
Replace TLSZ with TARGET_FMT_lx.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2444 c046a42c-6fe2-441c-8c8c-71466251a162
2007-02-20 23:37:21 +00:00
ths
b29a0341d7
EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2351 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-24 18:01:23 +00:00
ths
9c2149c8e0
Implementing dmfc/dmtc.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2348 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-23 22:45:22 +00:00
ths
5dc4b74480
Scrap SIGN_EXTEND32.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2251 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-21 13:48:28 +00:00
ths
c570fd169c
Preliminiary MIPS64 support, disabled by default due to performance impact.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2250 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-21 01:19:56 +00:00
ths
179e32bbcc
Fix erraneous fallthrough in MIPS trap implementation, thanks Atsushi Nemoto.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2247 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-16 16:45:18 +00:00
ths
ca7c2b1b9f
Handle invalid accesses as SIGILL for mips/mipsel userland emulation.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2235 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-10 22:08:10 +00:00
ths
71fb7241c6
Fix build of MIPS target without FPU support.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2233 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-07 20:07:37 +00:00
ths
aa328addc0
Fix reset handling, CP0 isn't enabled by default (a fact which doesn't
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matter when running in kernel space).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2228 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-07 16:22:15 +00:00
ths
e144966416
Simplify mask construction.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2227 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-07 00:30:19 +00:00
ths
bb8a53ad91
Update copyright notice.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2226 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-06 23:12:49 +00:00
ths
7a387fffce
Add MIPS32R2 instructions, and generally straighten out the instruction
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decoding. This is also the first percent towards MIPS64 support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2224 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-06 20:17:30 +00:00
ths
8c0fdd856c
Dynamically translate MIPS mtc0 instructions.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2223 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-06 18:19:33 +00:00