Paolo Bonzini
d6da1e9eca
event_notifier: cleanups around event_notifier_set_handler
...
Remove the useless is_external argument. Since the iohandler
AioContext is never used for block devices, aio_disable_external
is never called on it. This lets us remove stubs/iohandler.c.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-16 17:52:35 +01:00
Peter Maydell
2ccede18bd
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Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.9-pull-request' into staging
# gpg: Signature made Sat 14 Jan 2017 09:06:31 GMT
# gpg: using RSA key 0xF30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
# gpg: aka "Laurent Vivier <laurent@vivier.eu>"
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier/tags/m68k-for-2.9-pull-request:
target-m68k: increment/decrement with SP
target-m68k: CAS doesn't need aligned access
target-m68k: manage pre-dec et post-inc in CAS
target-m68k: fix gen_flush_flags()
target-m68k: fix bit operation with immediate value
m68k: Remove PCI and USB from config file
target-m68k: Implement bfffo
target-m68k: Implement bitfield ops for memory
target-m68k: Implement bitfield ops for registers
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-16 12:41:35 +00:00
Laurent Vivier
727d937b59
target-m68k: increment/decrement with SP
...
On 680x0 family only.
Address Register indirect With postincrement:
When using the stack pointer (A7) with byte size data, the register
is incremented by two.
Address Register indirect With predecrement:
When using the stack pointer (A7) with byte size data, the register
is decremented by two.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Thomas Huth <huth@tuxfamily.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1484332593-16782-6-git-send-email-laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Laurent Vivier
b19578f428
target-m68k: CAS doesn't need aligned access
...
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1484332593-16782-5-git-send-email-laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Laurent Vivier
308feb9352
target-m68k: manage pre-dec et post-inc in CAS
...
In these cases we must update the address register after
the operation.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1484332593-16782-4-git-send-email-laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Laurent Vivier
695576db2d
target-m68k: fix gen_flush_flags()
...
gen_flush_flags() is setting unconditionally cc_op_synced to 1
and s->cc_op to CC_OP_FLAGS, whereas env->cc_op can be set
to something else by a previous tcg fragment.
We fix that by not setting cc_op_synced to 1
(except for gen_helper_flush_flags() that updates env->cc_op)
FIX: https://github.com/vivier/qemu-m68k/issues/19
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1484332593-16782-3-git-send-email-laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Laurent Vivier
fe53c2be8c
target-m68k: fix bit operation with immediate value
...
M680x0 bit operations with an immediate value use 9 bits of the 16bit
value, while coldfire ones use only 8 bits.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1484332593-16782-2-git-send-email-laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Richard Henderson
a45f1763cc
target-m68k: Implement bfffo
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1479242669-25852-1-git-send-email-rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Richard Henderson
f2224f2c9a
target-m68k: Implement bitfield ops for memory
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1478699171-10637-6-git-send-email-rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Richard Henderson
ac815f46a3
target-m68k: Implement bitfield ops for registers
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1478699171-10637-5-git-send-email-rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Richard Henderson
86c9ab2776
target/arm: Fix ubfx et al for aarch64
...
The patch in 59a71b4c5b
suffered from a merge failure
when compared to the original patch in
http://lists.nongnu.org/archive/html/qemu-devel/2016-12/msg00137.html
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-13 09:48:20 -08:00
Peter Maydell
b6af8ea602
x86 and machine queue, 2017-01-17
...
Includes i386, CPU, NUMA, and memory backends changes.
i386:
target/i386: Fix bad patch application to translate.c
CPU:
qmp: Report QOM type name on query-cpu-definitions
NUMA:
numa: make -numa parser dynamically allocate CPUs masks
Memory backends:
qom: remove unused header
monitor: reuse user_creatable_add_opts() instead of user_creatable_add()
monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends
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Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging
x86 and machine queue, 2017-01-17
Includes i386, CPU, NUMA, and memory backends changes.
i386:
target/i386: Fix bad patch application to translate.c
CPU:
qmp: Report QOM type name on query-cpu-definitions
NUMA:
numa: make -numa parser dynamically allocate CPUs masks
Memory backends:
qom: remove unused header
monitor: reuse user_creatable_add_opts() instead of user_creatable_add()
monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends
# gpg: Signature made Thu 12 Jan 2017 17:53:11 GMT
# gpg: using RSA key 0x2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6
* remotes/ehabkost/tags/x86-and-machine-pull-request:
qmp: Report QOM type name on query-cpu-definitions
numa: make -numa parser dynamically allocate CPUs masks
target/i386: Fix bad patch application to translate.c
monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends
monitor: reuse user_creatable_add_opts() instead of user_creatable_add()
qom: remove unused header
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-13 14:38:21 +00:00
Peter Maydell
b6c08970bc
TriCore FPU patches
...
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Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-2017-01-11-2' into staging
TriCore FPU patches
# gpg: Signature made Wed 11 Jan 2017 13:40:11 GMT
# gpg: using RSA key 0x0AD2C6396B69CA14
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>"
# Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E 6E37 0AD2 C639 6B69 CA14
* remotes/bkoppelmann/tags/pull-tricore-2017-01-11-2:
target-tricore: Add updfl instruction
target-tricore: Added new JNE instruction variant
target-tricore: Added new MOV instruction variant
target-tricore: Added MADD.F and MSUB.F instructions
target-tricore: Added FTOUZ instruction
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-12 18:29:49 +00:00
Eduardo Habkost
8ed877b784
qmp: Report QOM type name on query-cpu-definitions
...
The new typename attribute on query-cpu-definitions will be used
to help management software use device-list-properties to check
which properties can be set using -cpu or -global for the CPU
model.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <1479320499-29818-1-git-send-email-ehabkost@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-01-12 15:51:36 -02:00
Doug Evans
410e98146f
target/i386: Fix bad patch application to translate.c
...
In commit c52ab08aee
,
the patch snippet for the "syscall" insn got applied to "iret".
Signed-off-by: Doug Evans <dje@google.com>
Message-Id: <f403045cde4049058c05446d5c04@google.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-01-12 15:51:35 -02:00
Bastian Koppelmann
50788a3fdb
target-tricore: Add updfl instruction
...
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-11 14:37:37 +01:00
Peer Adelt
dedd8c9c32
target-tricore: Added new JNE instruction variant
...
If D[15] is != sign_ext(const4) then PC will be set to (PC +
zero_ext(disp4 + 16)).
[BK: fixed style errors]
Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
Message-Id: <1465314555-11501-5-git-send-email-peer.adelt@c-lab.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2017-01-11 14:37:28 +01:00
Peer Adelt
550929dd46
target-tricore: Added new MOV instruction variant
...
Puts the content of data register D[a] into E[c][63:32] and the
content of data register D[b] into E[c][31:0].
[BK: fix style error]
[BK: Allocate temporaries only when needed]
Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
Message-Id: <1465314555-11501-4-git-send-email-peer.adelt@c-lab.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2017-01-11 14:37:15 +01:00
Bastian Koppelmann
ddd7fead8c
target-tricore: Added MADD.F and MSUB.F instructions
...
Multiplies D[a] and D[b] and adds/subtracts the result to/from D[d].
The result is put in D[c]. All operands are floating-point numbers.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-11 14:37:07 +01:00
Bastian Koppelmann
8f75983db8
target-tricore: Added FTOUZ instruction
...
Converts a 32-bit floating point number to an unsigned int. The
result is rounded towards zero.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-11 14:36:51 +01:00
Richard Henderson
4885c3c495
target-i386: Use ctpop helper
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:49:59 -08:00
Richard Henderson
3253cddd21
target-tilegx: Use ctpop helper
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:49:59 -08:00
Richard Henderson
08da3180dc
target-sparc: Use ctpop helper
...
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:49:55 -08:00
Richard Henderson
250a87d556
target-s390x: Avoid a loop for popcnt
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:48:57 -08:00
Richard Henderson
7977000220
target-ppc: Use ctpop helper
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:48:57 -08:00
Richard Henderson
de26a584d2
target-alpha: Use ctpop helper
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:48:56 -08:00
Richard Henderson
3946c6aa3d
target-xtensa: Use clrsb helper
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:47:48 -08:00
Richard Henderson
16256947eb
target-tricore: Use clrsb helper
...
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:47:48 -08:00
Richard Henderson
bc21dbcc12
target-arm: Use clrsb helper
...
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:47:48 -08:00
Richard Henderson
e5143c9088
target-i386: Use clz and ctz opcodes
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
7539a012f6
target-arm: Use clz opcode
...
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
b79ea941d6
target-xtensa: Use clz opcode
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
03a733dc62
target-unicore32: Use clz opcode
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
0efa820854
target-tricore: Use clz opcode
...
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
c3aa369e5d
target-tilegx: Use clz and ctz opcodes
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
0f9712b117
target-s390x: Use clz opcode
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
9b8514e56e
target-ppc: Use clz and ctz opcodes
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
555baef8d0
target-openrisc: Use clz and ctz opcodes
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
1a0196c5c7
target-mips: Use clz opcode
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
5318420c62
target-microblaze: Use clz opcode
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
272694a29d
target-cris: Use clz opcode
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
881549da4b
target-alpha: Use the ctz and clz opcodes
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
f6156b8fb0
target-s390x: Use the new deposit and extract ops
...
Use the new primitives for RISBG.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:10 -08:00
Richard Henderson
7b4d326f47
target-ppc: Use the new deposit and extract ops
...
Use the new primitives for RDWINM and RLDICL.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:10 -08:00
Richard Henderson
6eebb7a438
target-mips: Use the new extract op
...
Use extract for EXT and DEXT.
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:10 -08:00
Richard Henderson
04fc2f1c8f
target-i386: Use new deposit and extract ops
...
A couple of places where it was easy to identify a right-shift
followed by an extract or and-with-immediate, and the obvious
sign-extract from a high byte register.
Acked-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:10 -08:00
Richard Henderson
59a71b4c5b
target-arm: Use new deposit and extract ops
...
Use the new primitives for UBFX and SBFX.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:10 -08:00
Richard Henderson
f49f1ae73b
target-alpha: Use deposit and extract ops
...
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:10 -08:00
Peter Maydell
dbe2b65566
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-----END PGP SIGNATURE-----
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.9-pull-request' into staging
# gpg: Signature made Tue 27 Dec 2016 17:52:12 GMT
# gpg: using RSA key 0xF30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
# gpg: aka "Laurent Vivier <laurent@vivier.eu>"
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier/tags/m68k-for-2.9-pull-request:
target-m68k: free TCG variables that are not
target-m68k: add rol/ror/roxl/roxr instructions
target-m68k: Inline shifts
target-m68k: Do not cpu_abort on undefined insns
target-m68k: Implement 680x0 movem
target-m68k: add cas/cas2 ops
target-m68k: add abcd/sbcd/nbcd
target-m68k: add 680x0 divu/divs variants
target-m68k: add 64bit mull
target-m68k: add cmpm
target-m68k: Split gen_lea and gen_ea
target-m68k: Delay autoinc writeback
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-28 17:11:11 +00:00
Laurent Vivier
2b5e217067
target-m68k: free TCG variables that are not
...
This is a cleanup patch. It adds call to tcg_temp_free()
when it is missing.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27 18:28:40 +01:00